A timing ECO should be power, performance and area aware and that was the crux of this webinar, where we discussed several strategies about how to do effective ECO as an expert .Slack based ECO is a beautiful strategy which helps you to achieve your timing target, while helping you to reduce on power and areaContinue reading
A PPA card like the above, is something which every VLSI engineer should be carrying like a business card. Why? Right from RTL to synthesis to PNR to signoff, we do things like upsize, downsize, VT swap, and many more, and all these factors impacts or tweaks your design PPA in one way or the other.
Let’s take an example of ‘downsize’
Hello ….lets continue from here So I have been bragging about that ‘art of layout’ is a combination of euler’s path and stick diagram. But you need a proof why am I saying that Let’s first find out what happens if we decide to go only by stick diagram and […]Continue reading
Hello I wrote about euler’s path and stick diagram in two different blogs, but now is the time to show you how are they connected. It’s simple and, seems, they can’t be separated out from each other. To prove that, let’s take a random logic using the below pull-up network…… […]Continue reading