History etched with VSDOpen2018 – First VLSI online conference….
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
Tag Archives: Alberto Gomez Saiz
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Paper 4: Rapid Physical Implementation and Integration using eFabless platform
This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform [1]. The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider
Rapid Physical IC Implementation
“Rapid Physical IC Implementation and Integration using Efabless Platform”. This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform
