The propagation delay of a logic gate e.g. inverter is the difference in time (calculated at 50% of input-output transition), when output switches, after application of input.

In the above figure, there are 4 timing parameters. Rise time (t_{r}) is the time, during transition, when output switches from 10% to 90% of the maximum value. Fall time (t_{f}) is the time, during transition, when output switches from 90% to 10% of the maximum value. Many designs could also prefer 30% to 70% for rise time and 70% to 30% for fall time. It could vary upto different designs.

The propagation delay high to low (t_{pHL}) is the delay when output switches from high-to-low, after input switches from low-to-high. The delay is usually calculated at 50% point of input-output switching, as shown in above figure.

Now, in order to find the propagation delay, we need a model that matches the delay of inverter. As we have seen above, the switching behavior of CMOS inverter could be modeled as a resistance R_{on} with a capacitor C_{L}, a simple first order analysis of RC network will help us to model the propagation delay.

## First order RC network

Consider the following RC network to which we apply a step input.

Our aim is to find ‘t’ at Vdd / 2.

Vout = (1-e^{-t/τ}) Vdd, where τ = RC = time constant.

Substituting ‘Vout’ equal to Vdd/2, and ‘t’ equal to ‘tp’ in above equation, we get the following :

Vdd/2 = (1-e^{-tp/τ}) Vdd

Therefore, t_{p} = ln(2) τ = 0.69τ

Hence, t_{p} = 0.69RC

Hence, a CMOS inverter can be modeled as an RC network, where

R = Average ‘ON’ resistance of transistor

C = Output Capacitance

# Engineering Change Order (ECO)

_{L}) of an inverter is constant, and the input slew is varying.

**“Delay reduces with increase in input transition and constant load capacitance”**

**“Delay increases with increase in output capacitance and constant input transition”**

**input transition and output capacitance**.

**“Delay varies by varying drive-strength (ON resistance) of the logic cell”**

**“Delay can be reduced by using low Vt cells, but the cost paid is high leakage power”**

**Check out related course:**

#### Circuit Design & SPICE Simulations – Part 1

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