Opensource hierarchical physical design update on RISC-V SoC

At first, they will ask, why you’re doing it? Later they’ll ask, how you did it?

And I am sure, that will also be the case with hierarchical physical design flow using end-to-end opensource EDA tools

Hey There,

Few months back, I had posted the below floorplan of picoSoC, which is a simple (yet powerful) example of SoC using picoRV32, which can run code directly from SPI flash chip and can be used as a turn-key solution for trivial tasks in ASIC and FPGA designs

Last couple of weeks, me and Tim Edwards have been working very hard on implementing the above chip using hierarchical feature of open-source EDA tool. And you know what? Hierarchical physical design never existed before for open-source EDA tools, until yesterday.

That’s the beauty, when someone asks me “Why are you doing it?”

Hierarchical PD using commercial EDA tools – Verified, tested, taped-out, done

Hierarchical PD using open-source EDA tools – Evolving

As per my experience, anything which is “evolving” and has an army of committed people supporting it, has a future. And its bright. Try investing time and money, early

Let me prove it to you.

As I said above, just few weeks back, a hierarchical open-source PD flow never existed. But today, below is how it looks like:

We were able to successfully place and route the blocks and above is the view from (again) an open-source layout tool Magic. There are couple of fixes and upgrades that needs to go in, to place the blocks where we want it to be. But just think about it for a moment, within weeks, if we can achieve this, what will happen in upcoming months? What will be its status in upcoming years? I will tell you what it would be

Very soon, I will show you how to place/route/tape-out a complex RISC-V SoC like E31 (in below image) using all open-source EDA tools and 28nm foundry process