VSD Intern – Mixed Signal Physical Design Flow

Mixed signal Physical Design labs using OpenLANE/Sky130


This course describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, OpenLANE. It also discusses the steps to modify the current IP layouts in order to ensure its acceptance by the EDA tools

Mixed signal SoC is a chip which contains both analog and digital blocks. The designers are adding more analog circuitry and increasing their complexities day by day. Not only that, they also contain digital control logic. As the process nodes shrink, the demand for integration grows. A divide and conquer approach is followed, where the analog and digital structures were dealt with separately. Usually, an analog IP (Intellectual Property) is bought as black- box

To implement a RTL-to-GDS flow for mixed signal SoC, there is need to establish communication between the analog and digital blocks. For this integration to happen, hierarchical level of abstraction with either analog or digital as top level is required. In order to carry out this task, OpenROAD project can be utilized

Hope you enjoy the session. Any constructive feedback is appreciated


  • Generating hard-macro LEF for basic analog block
    • Introduction to mixed-signal flow and EDA tools used
    • Macro LEF file modification
    • Steps to create pins in macro LEF
    • Steps to modify LEF class, origin and site properties
    • Steps to modify LEF bounding box property
    • Steps to modify LEF port property
  • Macro based RTL2GDS using OpenLane/Sky130
    • Steps to setup new OpenLANE projec
    • Steps to setup input files in OpenLANE project
    • Steps to setup macro LEF files for OpenLANE flow
    • Final OpenLANE config file setting
    • Prep design and add LEFs in OpenLANE flow
    • LEF file modifications summary
  • RTL2GDS Physical Design flow steps
    • Short theory on RTL2GDS flow
    • RTL synthesis and floorplan step
    • Global and detailed placement
    • Tap-Decap detailed placement
    • PDN generation
    • Final routing and GDS generation
    • Final layout review and conclusion

Audience Profile

  • Students looking for a platform to enter into Physical design world
  • Experts looking forward to explore Macro based OpenLANE flow


  • VSD – Physical Design Flow course on Udemy
  • VSD – Custom layout course on Udemy

What you’ll learn

  • Multi-height RTL2GDS flow for Mixed Signal SoC
  • Steps to convert basic analog block to hard-macro
  • Steps to use hard-macro in OpenLANE RTL2GDS flow
  • Labs to verify Macro based Physical Design flow

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