On-Chip Clock Multiplier (PLL) on OSU180

This course will be an in-depth introduction to On-Chip Clock Multiplier (PLL) design and layout using open-source EDA tools (ngspice & Magic) on OSU180nm. This course starts with fundamentals (from CMOS inverter & basic semiconductor physics) to Advanced IP design Process, issues & ways to deal with them (by live demo of entire IP from Design to Layout).

Anyone who finds VLSI interesting & want to start his/her journey on this wonderful path can find lamp posts laid out for you in a way you can build your own IP after attending this course sincerely.

  • Introduction – Basics of IP, ASIC Design flow, On-chip clock Multiplier, PLL,
  • Theory & fundamental Concepts – CMOS implementation, transistor sizing, 2nd order control system, IC fab process, Euler path.
  • Pre-layout Implementation (lab session) – setting up system with linux, installation of tools, IP design, simulation & verification
  • Post-layout Implementation (lab session) – device to block level layout, extracting parasitic capacitors, simulation & verification.
  • Summary & Conclusion – Review Results, Future work, Acknowledgement.


Format: Cloud based Virtual Training Workshop

Duration - 1 Day

Cost : $25

Date : 9 January 2022

Registration  :  Enroll Here

For more information: vsd@vlsisystemdesign.com