On-Chip Clock Multiplier (PLL) on OSU180
This course will be an in-depth introduction to On-Chip Clock Multiplier (PLL) design and layout using open-source EDA tools (ngspice & Magic) on OSU180nm. This course starts with fundamentals (from CMOS inverter & basic semiconductor physics) to Advanced IP design Process, issues & ways to deal with them (by live demo of entire IP from Design to Layout).
Anyone who finds VLSI interesting & want to start his/her journey on this wonderful path can find lamp posts laid out for you in a way you can build your own IP after attending this course sincerely.
- Introduction – Basics of IP, ASIC Design flow, On-chip clock Multiplier, PLL,
- Theory & fundamental Concepts – CMOS implementation, transistor sizing, 2nd order control system, IC fab process, Euler path.
- Pre-layout Implementation (lab session) – setting up system with linux, installation of tools, IP design, simulation & verification
- Post-layout Implementation (lab session) – device to block level layout, extracting parasitic capacitors, simulation & verification.
- Summary & Conclusion – Review Results, Future work, Acknowledgement.
On-chip clock multiplier (PLL) using OSU 180nm PDK
- Introduction
- Theory and fundamental concepts
- Pre-layout Implementation & simulation
- Physical Design introduction
- PFD and VCO PD
- Frequency Divider and MUX PD
- Final PLL layout and Conclusion
- ngSpice,
- Magic,
- OSU 180nm
Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 41 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 40,000+ students around 151 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques.
Refund Policy: If you are not able to join workshop, Last date to apply for refund is 8 January 2022 11:59 PM IST.
For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/
