VSD - Timing ECO (engineering change order) webinar
First, let’s define better? Better in terms of Power. Performance and Area
Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.
All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….
It’s time to unveil more than 9 strategies to do timing ECO and below are few of them
- Routing congestion aware timing ECO
- Path based analysis ECO for selected endpoints
- Replicated modules based timing ECO
- Legalized timing ECO
- Margin based timing ECO
See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)
- Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
- Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"
- You should have completed STA-1, STA-2 and Physical Design course atleast 50%
- You should understand basic timing analogies like setup time and hold time
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