VSD - TCL programming - From novice to expert - Part 2

Overview

This course is a unique mixture of TCL programming being used in manipulating output EDA tools, creating EDA commands (like call_timer, read_sdc, and many more) and generating output timing summary report. The concept of this course can be extended to create any command, moreover, create any kind of UI you wish to.

Build TCL scripts on their own from scratch
Build their own UI (user-interface)
Build their own procs and commands

This course will be more memorable one, as its a "first-of-its-kind" "state-of-the-art" unique blending of TCL with EDA.

Objective

Introduction to Yosys synthesis tool usage
- Example of a memory module RTL description
- Memory functionality and Synthesis using Yosys
- Components and Gate level netlist description of Snthesized memory
- Memory Write operation discussed in detail
- Memory Read operation and TCL scripting agenda
Hierarchy check and error handling script creation for Yosys
- Script to do hierarchy check
- Demo for hierarchy check script generation
- Error handling script for hierarchy check
- Demo for error handling script
Synthesis main file scripting and output file editing
- Synthesis script creation and demo
- Need and script to edit yosys output netlist
- Demo to edit output netlist and Introduction to 'procs'
World of 'Procs'
- Redirect stdout proc and demo of TCL array command
- 'set_multi_cpu_usage' proc
- Demo for 'set_multi_cpu_usage' proc
- read_lib and read_verilog proc demo
read_sdc proc - interpret clock generation constraints
- Read SDC file and replace square brackets by 'null'
- Evaluate clock period and clock port name from processed SDC
- Evaluate duty cycle and create clock in opentimer format
- Demo to convert constraints from SDC format to opentimer format
read_sdc proc - interpret IO delays and transition constraints
- Grep clock latency and port name from SDC file
- Convert set_clock_latency SDC to opentimer format
- Demo to convert set_clock_latency in SDC to arrival_time in opentimer
- Script and demo convert transition and input delay to opentimer format
- Script and demo to convert output SDC constraints to opentimer format
Process bussed ports and configuration file creation
- Script to expand bussed input ports for arrival time constraints
- Script and demo to convert all bussed constraints to bit-blasted
- Opentimer configuration file creation
Quality of results (QOR) generation algorithm
- Script to obtain STA runtime
- Script to obtain WNS and FEP for reg2out violations
- Script and demo for instance count, WNS and FEP for setup and hold
- Script and demo for report formatting

Audience Profile

Anyone who wishes to build his/her UI and learn TCL programming from basics
Anyone who wants to learn basics of RTL synthesis
Anyone who wants to learn basic programming algorithm and data flow

Prerequisites

TCL Programming - Part 1 needs to completed atleast 50%
Yosys synthesis tool needs to be installed

Tools Used

TCL scripts, (Tool Command Language) is a very powerful but easy to learn dynamic programming language

Shell script is a computer program designed to be run by the Unix shell, a command-line interpreter

Yosys is open source framework for Verilog RTL synthesis

Opentimer open source tool developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA

Qflow – Tool chain (like Yosys, Graywolf) for complete RTL2GDS flow