VSD - TCL programming - From novice to expert - Part 1

Overview

Be it learning scripting language or an EDA tool, nothing beats 'concepts'. I have been proving this in my courses, how learning a tool is the last 5% task of entire learning flow.My students, who have been working with on several projects and also learning through my courses, have not only learned semiconductors, but lived the journey. And I promise, the same will happen with my this course on TCL scripting as well.I have been using the same approach in last 10 years for solving problems, be it a TCL script issue or an issue with STA timing violation or an issue with DRC or an issue with floor planning or an issue with routing congestion, you name it..You will witness the same in all my courses and in this one as well. Let's unveil the concepts of data flow and manipulation using TCL scripts.

Build TCL scripts on their own from scratch
Build their own UI (user-interface)
Build their own procs and commands

Objective

Introduction to TCL task
- Introduction to sub-task
Sub-Task One : VSDSYNTH Toolbox usage scenarios
- Scenario 1 - User doesn't provides input csv file
- Scenario 2 & 3 - User providing incorrect csv OR typing "-help"
Sub-Task Two - From CSV to format[1] and SDC - Variable Creation
- Various tasks involved in format conversion
- openMSP430_design_details.csv
- Auto-Create variables using matrix and arrays
- Initialize variables for auto-creation variables task
- Auto creation of first variable - DesignName
- Auto creation of variables complete
- Variable Creation DEMO using TCL
Sub-Task Two - From CSV to format[1] and SDC - Processing constraints,csv
- Checking existence of files and folders mentioned in design_details.csv
- Convert constraints.csv file to a matrix object
- Compute row number using complex matrix processing
- DEMO for computing row numbers
Sub-Task Two - From CSV to format[1] and SDC - Processing clock constraints
- Algorithm to identify column number for clock latency constraints
- Start writing clock latency constraints in SDC file
- Complete clock latency constraints and clock slew constraints in SDC file
- Code to create clock constraints with clock period and duty cycle
- DEMO for creating complete clock constraints
Sub-Task Two - From CSV to format[1] and SDC - Processing input constraints
- Introduction to task of differentiating between bits and bus
- Algorithm to categorize input ports as bits and bussed
- File access and pattern creation steps
- Regular expression and regular substitute to get fixed space strings
- Demo for grepping input ports from all verilogs and reformatting for fixed space
- Read, split, uniquify, sort and join input ports to remove duplication
- Evaluate length of string and Demo of bits/bussed differentiation script
- Demo for input constraints generation and bits/bussed differentiation
Full script for download and Conclusion
- Constraints generation logic for output port and Conclusion!!

Audience Profile

Anyone who wants to do TCL programming
Anyone who wants to learn basic programming algorithm and data flow
Anyone who wants to code

Prerequisites

You should be able to understand basic UNIX commands like vim, ls -ltr, etc.
You should have a virtual machine with UNIX and TCL running, if using a Windows laptop
You should be able to install any linux package