VSD - Static Timing Analysis - II

Objective

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.

Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more.

Objective

Introduction to sta-2 and opentimer tool
- Introduction to sta-2
- Introduction to opentimer, netlist definition and my_run.tcl creation
Constraints creation commands for Opentimer
- Clock creation and clock arrival time definitions
- Input delay constraints for interface setup/hold analysis
- Clock slew and data slew constraints
- Output load and output delay constraints
- my_run.tcl for above experiments
Full reg2reg analysis using OpenTimer tool
- Actual arrival time (AAT) and required arrival time (RAT) calculation basics
- my_netlist.v
- my_netlist.timing
- Slack compute, pesimissim (cppr) and engineering change order (eco)
- updated my_netlist.v
- updated my_netlist.timing
- blank.spef
Interface analysis
- Introduction to interface analysis
- Case1 : C2Q and combinational delay for input is known
- Case2 : Input waveform specifications given
- Case 3 : setup_time, hold_time and combinational delay for output is known
- Hold fixing ECO and Case 4: Output waveform specifications known
- updated my_netlist.v and hold eco script for above interface analysis
- Case 5 : Source synchronous interface analysis for setup
- Source synchronous interface setup analysis in Opentimer tool
- Source synchronous interface hold analysis
Clock gating analysis
- Introduction to clock gating analysis
- Active high clock gating analysis
- Active low clock gating analysis
- Latch based clock gating technique
- Integrated clock gating (ICG) cell
Asynchronous and data checks
- Inception of asynchronous reset design technique
- How reset synchronizers resolves reset desertion
- Data-to-data setup and hold check
- Sequential and clock tree min pulse width check
Latch timing and load/slew analysis
- Introduction to positive and negative latch behavior
- Reg2Latch path with 'time borrow' and 'time given' examples
- Introduction to different kinds of power
- (Snippet for CTS course) Load and slew inter-dependence
Quiz & Labs

Audience Profile

Anyone who has completed static timing analysis - part 1 course
Anyone (with 100% static timing analysis - part 1 course completed) who has basic knowledge on flipflops, gates and digital logic

Prerequisites

Static Timing analysis - part 1 course needs to be fully completed to start this course. No exceptions
Knowledge of physical design flow and clock tree synthesis will be helpful

Tools Used

"Opentimer" open source tool developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA