VSD - Static Timing Analysis - I


Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details.


  • Introduction and agenda
    • Introduction to timing path and arrival time
    • Introduction to required time and slack
    • Introduction to basic categories of setup and hold analysis
    • Introduction to data check and latch timing
    • Introduction to slew, load and clock checks
  • First things first - Introduction to timing graph

    • Convert logic gates into nodes
    • Compute actual arrival time (AAT)
    • Compute required arrival time (RAT)
    • Compute slack and introduction to GBA-PBA analysis
    • Convert pins to nodes and compute AAT, RAT and slack
  • Clk-to-q delay, library setup, hold time and jitter

    • Introduction to transistor level circuit for flops
    • Negative and positive latch transistor level operation
    • Library setup time calculation
    • Clk-q delay calculation
    • Steps to create eye diagram for jitter analysis
    • Jitter extraction and accounting in setup timing analysis
  • Textual timing reports and hold analysis
    • Setup analysis - graphical to textual representation
    • Hold analysis with real clocks
    • Hold analysis - graphical to textual representation
  • On-chip variation
    • Sources of variation - etching
    • Sources of variation - oxide thickness
    • Relationship between resistance, drain current and delay
  • OCV timing and pessimism removal
    • OCV based setup timing analysis
    • Setup timing analysis after pessimism removal
    • OCV based hold timing analysis
    • Hold timing analysis after pessimism removal
  • Quiz and Assessment

Audience Profile

  • Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough


  • Knowledge on physical design flow will be good to have
  • If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world

Tools Used

"OpenTimer" open source tool for Timing analysis

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