VSD - SoC Design of the PicoRV32 RISCV micro-processor

Overview

In this course we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible?

• Run a full physical design flow from RTL design to GDSII, making it ready for tape-out.

• For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company. Assignment submission is a must.

Objective

• Introduction to webinar

• efabless interactive tutorial

  • Introduction to webinar and SPI design selection for physical design
  • Introduction to efabless platform and webinar agenda
  • LIVE QnA with participants and steps to login to efabless marketplace

• CloudV interactive tutorial

  • Introduction to CloudV application
  • Steps to synthesize to target process and export to open-galaxy
  • Steps to import synthesized netlist into open-galaxy
• Synthesis flow interactive tutorial
  • Steps to start synthesis flow tool and run synthesis
  • Pin arrangement UI and automatic grouping of vectors
  • Few tips on pin-placement and floor-planning chip
  • LIVE QnA with participants regarding pacement and STA
  • Routing post-route STA and LVS check
• LVS & DRC
  • Steps to fix LVS, Magic short-cut keys and run DRC
  • LIVE QnA with participants on LVS and steps to fix DRC
  • DRC cleaning steps LIVE and QnA with partcipants on DRC
  • LIVE QnA with participants about future of qflow and efabless
• Full chip integration in open-galaxy
  • Steps to create a new project for floorplanning and integration
  • Steps to populate layout from library manager and select SPI block
  • Steps to select, generate copies and arrange pad frames
  • Steps to abut pads and ensure pad-frame is DRC clean
• Signal routing
  • 'reset' signal routing steps
  • sck, csb, other signal routing and DRC clean step
  • Dynamic power estimation and power routing
  • Tie-down unused inputs, add substrate contacts and antenna diodes
  • Add pin labels, review completed layout and final LVS check
• Challenge description and mode of submission

Audience Profile

• Anyone curious to know end-to-end aspects of chip designing i.e from SOC design to tapeout, which involves lot of steps like placement, routing, clock tree synthesis, DRC cleanup, LVS fixing
• Anyone curious to know how to achieve all of above using all EDA open-source tools. Not a single penny to be paid as license fee
• Anyone who wishes to innovate, implement and submit a paper on any design, implemented using open-source tools

Prerequisites

• Knowledge about previous course "VSD - Making the Raven chip: How to design a RISC-V SoC" is nice to have, but not must to have as this course focuses on Physical design concepts, like synthesis, placement, routing, DRC, LVS and tapeout needs
• Knowledge about clock tree synthesis/STA/custom layout is nice to have and can be taken from existing VSD courses Udemy. Take up the courses "VSD - clock tree synthesis", "VSD - Static timing analysis" and "VSD - Custom Layout" on Udemy

Tools Used

Qflow –  Tool chain (like Yosys, Graywolf) for complete RTL2GDS flow

Buy the course :

VSD - SoC Design of the PicoRV32 RISCV micro-processorKunal Ghosh, Tim EdwardsFreedom to build micro-processors₹1,799₹499 3.6 (63 ratings)28 lectures, 4 hours