VSD - RTL Synthesis Q&A Webinar

Overview

Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf.Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)

Students will get structured answers to queries which they might otherwise find difficult to search online
Perception about synthesis and opensource tools will change
Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore

Objective

Introduction
Queries next stage RTL design, HDL and asynchronous logic synthesis answered
Query on best way to do synthesis answered
Queries on ideal clock, synthesis challenges across nodes and multiple clock
Queries on synopsys lib file reading and synthesis constraints answered
Queries on partitioning, power estimation and power efficient RTL answered
Queries on testbench for maximum coverage and physical aware Yosys answered
Yosys project start-up story answered
Queries on testbench for maximum coverage and physical aware Yosys answered
Yosys project start-up story answered
Queries on machine learning in Yosys, handling scan logic and derates answered
Queries on next milestones of Yosys and fsm_recode command answered
Query on equivalence check and conclusion

Audience Profile

Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
Anyone looking to start using opensource tool Yosys for synthesis
Anyone curious to know what's happening in the world of RTL synthesis