VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a


RISC-V is a free and open RISC instruction set architecture. and was originally developed in Computer Science division of the EECS Department at the University of California, Berkeley This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples

The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain.

This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like "IMFD" will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses

Acknoledgements -

I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.

I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course.


  • Introduction
  • Course Content

    • From apps to hardware
    • Detailed description of course content with examples
  • Integer number representation

    • 64-bit number system for unsigned numbers
    • 64-bit number system for signed numbers
  • Application binary interface (ABI)
    • Introduction to application binary interface (ABI)
    • Memory allocation for doublewords - "little-endian"
    • Representation of load, add and store instructions with example
    • Concluding 'need' for 32-registers and their respective ABI names
  • Memory allocation and stack pointer
    • Introduction to 'jump and link' instruction
    • Unconditional jump using 'jalr' and introduction to stack pointer (sp)
    • From 'c' program to 'risc-v' ISA and introduction to pseudo instructions
    • Status of instruction address, program counter and stack pointer
  • Analyze assembly language program in RISC-V format
    • Instruction to store data from register to stack
    • Steps to jump to proc and return to main program using 'auipc' and 'jalr'
    • Steps to load user input from scanf procedure
  • Analysis of leaf and nested procedure
    • Load arguments and jump to leaf proc
    • Leaf proc execution
    • Retrieve return address (ra) and stack pointer (sp) register values
  • Conclusion and Assignment

Audience Profile

  • Anyone who wants to understand language of computer
  • Anyone who wants to learn processor architecture
  • Anyone who wants understand how apps run on chips inside computer


  • You should be familiar with binary numbers. This is anyways covered in brief

Tools Used

RISC-V GNU Compiler, is the RISC-V C and C++ cross-compiler. It supports two build modes:a generic ELF/Newlib toolchain and a more sophisticated Linux-ELF/glibc toolchain.

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