VSD - Pipelining RISC-V with Transaction-Level Verilog

Overview

Do you want to build just verilog models or high-quality verilog models in half the time?

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform

This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one.

Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
Build their own verilog models for IP's using a simpler and powerful Verilog design environment

Objective

Introduction of Steve Hoover
Launch of makerchip.com and introduction to webinar motive
- Live QnA with participants on webinar content and motive
RISC-V overview and instruction Pipelining Concepts
- Pipelined RISC-V block diagram description
- RISC-V waterfall diagram and hazards
- Live QnA with participants regarding processor architecture
IP design methodology
- RISC-V IP challenges and WARP-V development progress
- Why Transaction-Level verilog?
- Introduction to makerchip.com platform
Examples using makerchip.com platform
- More about makerchip.com and first exercise for participants
- Inverter exercise for participants and LIVE QnA about makerchip.com platform
- Sequential logic - Fibonacci series example
- LIVE QnA with participants regarding exercises
Pipelines
- Pythagoras theorem example of pipeline
- Retiming implementation in TL-Verilog vs system verilog
- Fibonnaci series pipeline and concept of validity
- Exercise to identify error conditions in WARP-V
Pipeline Interactions
- WARP-V operand mux
- Register bypass and time division multiplexing (TDM) example
- Solve TDM exercise - Part1
- Solve TDM exercise - Part2
- LIVE QnA with participants regarding pipeline interactions and other topics
Miscellaneous Topics
- Hierarchy and interfaces in TL-Verilog
- LIVE QnA with participants on WARP-V core
- Transaction flow and wrap-up course content
Certification challenge problem statement

Audience Profile

Anyone who wants to learn transaction-level verilog
Anyone who wants to stay ahead of curve in frontend VLSI
Anyone who wants to learn and implement pipelining concepts in field of computer architecture

Prerequisites

You should know basics of digital design like flip-flops, gates, clock, etc.
You should have finished RISC-V ISA - Part 1a course on Udemy if new to CPU microarchitecture
You should have a modern web browser like chrome, and login to Makerchip to ensure compatibility