VSD - Physical Design Flow


The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And shared our industrial experience to give the technological exposure of current development in chip world...

The lectures are accompanied by hands-on labs.


  • Physical Design Flow Overview
    • Floor-Planning Steps
    • Netlist Binding and Placement Optimization
    • Placement Timing and Clock Tree Synthesis
    • Clock Net Shielding
    • Route - DRC Clean - Parasitics Extraction - Final STA
  •  Floorplanning
    • Utilization Factor and Aspect Ratio
    • Concept of Pre-Placed Cells
    • De-coupling Capacitors
    • Power Planning
    • Pin Placement and Logical Cell Placement Blockage
  •  Placement
  • Net-list Binding and Placement
  • Optimize Placement Using Estimated Wire Length and Capacitance
  • Optimize Placement Continued
  • Timing Analysis with Ideal Clocks
    • Setup Timing Analysis and Introduction to Flip-Flop Setup Time
    • Introduction to Clock Jitter and Uncertainty
    • Setup Timing Analysis with Multiple Clocks
    • Multiple Clock Timing Analysis and Introduction To Data Slew Check
    • Data Slew Check
  • Clock Tree Synthesis and Signal Integrity
    • Clock Tree Routing and Buffering using H-Tree Algorithm
    • Crosstalk and Clock Net Shielding
    • Static Timing Analysis with Real Clocks
    • Hold Timing Analysis Concluded
    • Multiple Clocks Setup Timing Analysis with Real Clocks
  • Routing and Design Rule Check (DRC)
    • Introduction to Maze Routing - Lee's Algorithm
    • Lee's Algorithm Conclusion
    • Design Rule Check
  • Parasitics Extraction
    • Introduction to IEEE 1481 - 1999 SPEF format
    • SPEF Representation of a NET
    • Distributed Resistance and Capacitance Representation in SPEF
    • SPEF Header Description, Physical Design Flow Conclusion and What Next!!

Audience Profile

Students looking for entry in VLSI World and explore new ways of solving problems


Basic Digital Design

Tools Used


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