VSD - Online IP Design (VSD-OIPD)
VSD-OIPD is an "VSD - Online IP Design" program in collaboration with LibreSilicon, where its open for all students,designers/hobbyists looking to lean and contribute in open-source VLSI hardware domain. This program will use SKY130nm and LS1um pdk's for its execution.
If you are interested in VSD-OIPD, please complete this Google form: https://forms.gle/KeozkbMLhXgaXvdV6
VSD will review the applications and try to assign the most suitable project for participants.
Last date for application: 2 August 2020
Program will begin: 3 August 2020
Program Tenure: 8 weeks ( 3rd August -21st September 2020)
Prerequisite: Basic VLSI knowledge or good Software development knowledge is must to apply for this program.
VSD-Hardware Design Program
| Sr.no | Project Name | Project code |
|---|---|---|
| 1 | LVDS | LVDS |
| 2 | SERDES | SERDES |
| 3 | SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM) | SRAM |
| 4 | 10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference | ADC |
| 5 | OpenRoad RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, openroad RTL2GDS tools, outputs = GDSII) | RTL2GDS |
| 6 | Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up, Strength 4mA @ 3.3V, Normal, High noise (Fast speed) | BIDIBUFF |
| 7 | 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference | DAC |
| 8 | On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v | PLL |
| 9 | Lower power current programmable CMOS comparator with hysteresis | COMP |
| 10 | Open-source Layout Generator (Inputs = Digital or Analog Circuit, Output = Layout) (Ref:OpenRAM, LCLAYOUT) | LAYOUT |
| 11 | PadCell Pad | PAD |
| 12 | PadCell Router | ROUTER |
| 13 | PadCell ESD | ESD |
| 14 | PadCell Power Lanes + Pad Cell | LANES |
| 15 | PadCell Corner Cells | CORNER |
| 16 | PadCell Guard Rings | GUARD |
| 17 | PadCell Interface | IFCORE |
| 18 | PadCell Putting it all together | PADCELL |
| 19 | PadCell testing | PADTEST |
| 20 | PadCell characterization | PADCHAR |
| 21 | PadCell RTL2GDS flow support | PADFLOW |
| 22 | Test Wafer | TESTWAFER |
| 23 | RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for for LibreSilicon 1um Process Node | LSQFLOW |
| 24 | RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for SKY130 | SKYQFLOW |
| 25 | Reproducible Builds for OpenLane: Trying to reproducibly build a chip with qflow. Document all problems. Research reasons and possible countermeasures. Develop fixes | REPRODQFLOW |
| 26 | Reproducible Builds for TheOpenRoadProject/TheOpenLane | REPRODROAD |
| 27 | Process Node Map | PROCESSMAP |
| 28 | Research: Search for all+exotic standard cells | EXOTICCELL |
| 29 | C++: Parametric support for hierarchical sheets in EESchema, GUI+ Fileformat, for V6 | KICADPARAM |
| 30 | Recognize the function of a cell based on the netlist or the truth table | FUNCTIONID |
| 31 | DRC Test Generator for Good and Bad Examples | DRCEXAMPLE |
| 32 | LibreCell layout live preview (like graywolf) | LCLAYOUTLIVE |
| 33 | DRC Correction Engine: Analyze common DRC issues and try to write a tool that automatically detects them and solves them (while not making things worse 🙂 | DRCCORRECT |
| 34 | Popcorn growing | POPCORN |
| 35 | Improve Popcorn to grow cells automatically (without predefined their relationships in Makefiles) | POPCORNAUTO |
| 36 | Yosys Synthesis Segmentation for huge designs | SEGMENTATION |
| 37 | Datascience: LCLayout + LCTime Meta-Parameters | METAPARAM |
| 38 | Create a a tool that calculate number of stages from a Spice Netlist | CALCSTAGES |
| 39 | Liberty File HTML Report generation | LIBERTYHTML |
| 40 | Liberty File Comparison: Compare 2 different liberty files, report similarities and differences | LIBERTYDIFF |
| 41 | Generate a standard cell library for Path Programmable Logic / Asynchronous Logic | ASYNC |
| 42 | Synthesize a chip with Path Programmable Logic in qflow | ASYNCQFLOW |
| 43 | RISCV-Accelerators | RISCVACCEL |
| 44 | RISCV-MicroArch | RISCVMICRO |
| 45 | WARP-V (RV32IMF) SoC design with existing analog IP's | RISCVSOC |
| 46 | RTL2GDS with OpenLane with the standard cells from StdCellLib for Libresilicon 1um | LSLANE |
| 47 | RTL2GDS with OpenLane with the standard cells from StdCellLib for SKY130 | SKYLANE |
| 48 | OpenFPGA design for SKY130 | OPENFPGA |
| 49 | Raspberry PI for IOT | RASPBERRYIOT |
| 50 | Reproducible Builds for StdCellLib: Trying to reproducibly build a standard cell library. | REPRODCELL |
