VSD - Making the Raven chip: How to design a RISC-V SoC

Overview

Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

Students will be able to build and configure their own SoC (System-On Chip)
Students will be able to create their own defition of GPIO
Understand decision making process like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more

Objective

Introduction to webinar and instructors
- Where does this webinar fits in chip design flow?
- RISC-V basic introduction
efabless platform overview
- Webinar agenda and introduction to efabless.com
- efabless model for IP design and login steps to efabless platform
- Introductory interactive tutorial of efabless platform
Steps to characterize analog circuits
- Step to push IP for eg. level shifter to your opengalaxy account
- Set PVT conditions and simulate level shifter
- LIVE QnA with participants regarding efabless platform
Starting the RISC-V SoC Reference Design
- Pre-requisites and RISC-V, picorv32 and picoSoC overview
- Raven SoC and Raven full chip overview
- LIVE QnA regarding Raven full chip design
- Clone Raven chip into opengalaxy environment
Understanding the RISC-V SoC Reference Design
- Interactive tutorial file system and introduction to digital picorv32 core
- Digital UART and independent SPI module
- SRAM, analog peripherals, real valued verilog and pad-frame
- Voltage domain and LIVE QnA with participants regarding SoC reference design
Design choices
- Design goals and analog components
- Analog caliberation, GPIO, real-time monitoring and interrupts
- LIVE QnA with participants regarding design goals and components
- Memory map
Assembling the parts into a verilog top-level module
- SoC complete memory map and top level connections
- Analog configuration, control memory map, pads and C-code testbench
- C-code testbench and verilog testbench detailed explanation
- Interactive tutorial to run full Raven testbench suite
Making a new testbench
- Interactive tutorial to setup and make a new testbench
- Running and debugging testbench using GTKWave
- LIVE testbench debugging and re-configuring
- Modify the raven_soc verilog to include a timer module
Detailed assignment description and mode of submission

Audience Profile

Anyone who wants to learn SoC planning
Anyone who wants to learn chip design from specifications to Layout
Anyone curious to know, what happens before Synthesis, Physical design and STA

Prerequisites

A Linkedin login ID
Knowledge on RISC-V is nice to have, but not must to have
Digital design concepts and a bit of verilog syntax is nice to have

Tools Used

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364).

GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

Qflow – Tool chain (like Yosys, Graywolf) for complete RTL2GDS flow