VSD - Library characterization and modelling - Part 1


If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means. You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete.

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes. Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

  • Understand timing, noise and power libraries syntax and semantics
  • Develop models for logic gates and macros

  • Use the above generated models and do STA


  • Introduction and Need for characterization
  • Cell design and characterization flows

    • Inputs for cell design flow
    • Circuit design step
    • Layout design step
    • Typical characterization flow
  • General Timing characterization parameters

    • Timing threshold definitions
    • Propagation delay and transition time
    • Output current model and CCS table
    • Output voltage waveform and introduction to tristate buffer
    • Different transitions for tristate buffer
  • Timing characterization parameters for registers
    • Netlist connectivity for latch and flipflop
    • Library setup time as a function of data and clock transition time
    • True single phase clocked (TSPC) register for hold time evaluation
    • Library setup time for TSPC register
    • Hold time, recovery & removal time evaluation
  • Noise characterization and modelling
    • Introduction to noise - Crosstalk glitch and delta delay
    • Introduction to channel connected components (CCC)
    • ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current
    • Need of dc_current attribute
    • Noise immunity curve, propagated_noise_high and propagated_noise_low
    • stage_type attribute and need for tie_hi cells
    • Miller cap, arc based ccs noise model and full noise library
  • Power characterization and modelling
    • Static power - Subthreshold current and junction leakage current
    • Static power - Tunnelling current
    • Internal leakage power - leakage_current and leakage_power groups
    • Internal leakage power - cell_leakage_power & Tunneling curent - gate_leakage
    • Dynamic power - Switching current
    • Dynamic power - Short-circuit current
    • Switching power and short-circuit power modelling
    • Hidden power concept and modelling
  • Timing modelling
    • Groups and attributes
    • Library group and its attributes
    • Cell groups and combinational function pin groups
    • Flip-flop modelling using 'ff' group
    • Latch modelling using 'latch' group
    • Introduction to 'statetable' and latch description using 'statetable' group
    • Flip-flop modelling using 'statetable' group and introduction to 'driver model'
  • Driver model, receiver model and conclusion

Audience Profile

  • Research professionals
  • Graduate students
  • Circuit and PDK designers
  • Characterization engineers
  • CAD developers
  • Managers, Mentors and the merely curious


  • Full knowledge on circuit design and SPICE simulations
  • Full knowledge on custom layout
  • Nice to have knowledge on Physical design, Static timing analysis, Noise & Crosstalk and Clock tree synthesis
  • You can refer to my existing courses or any other external material, but knowledge about above all is a must

Tools Used

State-of-the-art characterization software "GUNA"

Liberty is a registered trademark of Synopsys Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SDF and SPEF are trademarks of Open Verilog International

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