FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

Overview

This webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.

VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

• "Innovation at its best"

Objective

• Introduction
• Mixed Signal SoC details with RISC-V core and PLL IP
  • RVMYTH RISC-V Core
  • Transaction level Verilog
  • Why FPGAs ?
  • Makerchip platform
  • TL - Verilog to RTL verilog
  • Functional Simulation using iverilog
• Mixed Signal FPGA flow
  • FPGA - Steps to create project
  • FPGA - Steps to generate IPs
  • FPGA - RTL simulation
  • FPGA - Synthesis
  • FPGA - Implementation and timing analysis
  • FPGA - Bit-stream generation, FPGA programming and ILA
• Conclusion and Assignment

Audience Profile

• Beginner in FPGA design
• Beginner in VLSI design
• Experienced Physical Design and STA engineers

Prerequisite

• VSD - RISC-V ISA course on Udemy
• VSD - Pipelining RISC-V using TL-Verilog course on Udemy

What you'll learn

• FPGA flow vs ASIC flow
• Basic mixed-signal RISC-V based SoC RTL design and simulations
• FPGA Synthesis, bit-stream generation and simulation

Buy the course :

VSD - Mixed-signal RISC-V based SoC on FPGAKunal Ghosh, Shivani ShahFPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP₹1,499₹449 4 (7 ratings)14 lectures, 1 hours