Introduction to Discrete Event Simulation Technology, Functional Verification, Getting acquainted with Simulation tools
Now here's a course, "hand-crafted" for anyone and everyone, who want to move from back-end to front-end OR for people just curious to know and learn, what exactly happens in field of VLSI verification. The reason its "hand-crafted" is because it starts from very basics and in coming parts of this course, things will slowly move towards advanced level UVM.
Another reason for this course to be "hand-crafted" is due to the open-source tool used to cover labs introduced in this course. This is Part - 1 in the "Verification Series". This part will cover SoC design flow, basics of functional verification, trends and challenges, introduction to open-source Embedded-UVM, emulation, and the DUT
Embedded UVM is an opensource implementation of IEEE 1800.2 standard of Universal Verification Methodology. In this webinar, we take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC-FPGA based Emulation.
Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.
- E-UVM Installation procedures
- Introduction to verification frame-work
- Introduction to Makefile concept and labs
- Introduction to functional spec and behavioral description
- Introduction to typical System-On-Chip
- Introduction to functional simulation and TLM simulation
- Basics of hardware, software, virtual platform and algorithms
- More information about virtual platforms
- Classification and conclusion of tasks involved in frontend and backend
- Verification Trends And Challenges
- Introduction to SoC FPGA
- Why the world needs more verification?
- Corollary of Moore's Law and its significance
- Repercussions of Moore's Law on verification
- Why the need of System Verilog and not Verilog ?
- Verification tool performance and take-aways
- Simulation vs Emulation and concept of multi-threading
- The need of the hour : Embedded-UVM
- Multi-core processor throughput vs latency and why E-UVM?
- More on multi-threading and world-wide initiatives on open-source verification
- More details and opportunities on open-source verification
- Present and future of programmable hardware
- How programmable hardware will be verified in future?
- Open-source hardware is not free
- Implications of FPGA in future
- Should be good with digital electronics
- Should be good with Linux/UNIX basic commands
What you'll learn
- SoC design flow, role of Functional Verification
- Logic Modeling, Introduction to Verilog
- Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
- Simulation Technology, Discrete Event Simulation
- Verification Trends and Challenges
- Concepts and Principles of Functional Verification
- Testbench Architecture and Components
- Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms
- Embedded UVM is currently the only UVM implementation that enables multicore testbench simulations
- Embedded UVM is optimized for multicore processors with each verification IP running on a parallel thread
- Embedded UVM simulates the testbench on separate threads running parallel to the design simulation
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