VSD - Embedded-UVM

Opensource Verification and Emulation

Overview

Of course, there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification trends and challenges which system Verilog and other verification platforms are not able to meet. So, we want to position Embedded-UVM for that. In the past decade or so, the major thing which is making verification tougher than it used to be, is the death of Moore’s law. As far as processor frequency goes, it stabilizes at 4GHz and it's coming down as we move to multi-core processors. So, when you look at it from a simulation perspective, post-2005 it is becoming increasingly difficult to run simulations on bigger chips.

Chip size keeps increasing, while processor speed is stagnant and hence, simulation is a limiting factor. Simulation speed is going to be limited unless we move to multi-core processors. Contemporary EDA tools run RTL simulations in a multi-core environment. System Verilog doesn’t run in a multi-core environment.Therefore, test-bench runs on one thread and RTL runs on multiple threads. RTL is more formal in nature, in sense, it can be synthesized, it can be partitioned, different partitions can run on different processors, while test-bench is behavioral in nature and it cannot be partitioned the way RTL can be.

Objective

Introduction
- Introduction to FPGA boards to be used in webinar
- Introduction to E-UVM framework using adder example
- Testcase and E-UVM download links
Verification trends and Challenges
- Verification perfomance and introduction to FOSSI
- Variation trends and challenges of data network and compute performance
- Testbenches for system level verification and hardware accelerators
- Hardware accelerators from verification perspective
- Hardware accelerators perspective Embedded - UVM
- LIVE QnA with participants about E-UVM multi-threading
- LIVE QnA regarding system-C comparison with E-UVM
Embedded UVM and Multicore test benches
- Introduction to Embedded-UVM
- Embedded-UVM innovation - Multicore UVM
- Multicore E-UVM implementation
Productivity and Emulation features
- Productivity features and interfacing with RTL simulations
- Embedded UVM powered emulation
- Testbench simulation demo with Avalon streaming bus as DUT
- OSI model of communication and UVM transaction explanation
Embedded UVM testbench Architecture and Environment
- Testbench architecture and verilog co-simulation
- Steps and importance of Randomizing object and cloning
- Typical UVM environment comparison in Embedded-UVM and system verilog
- LIVE QnA with webinar participants regarding E-UVM environment
- avst_keccak protocol
The DUT-SHA3 core
- Functional details, control & status, data map, output and input
- SHA3 core testbench understanding and running
- LIVE demo on DE10-Nano Cyclone V FPGA board
- LIVE code debug and emulation
Assignment explanation and conclusion
Assignment testcase download links

Audience Profile

Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology
Professional UVM engineers keen to know about multi-threaded testbench simulation technology
Anyone looking to learn new opensource technology and be ahead of market

Prerequisites

Basics of UVM is nice to have
Basics of digital design is a must to have
Novice knowledge of opensource EDA flow is nice to have

Tools Used

Embedded UVM is currently the only UVM implementation that enables multicore testbench simulations
Embedded UVM is optimized for multicore processors with each verification IP running on a parallel thread
Embedded UVM simulates the testbench on separate threads running parallel to the design simulation