VSD - Custom Layout


Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format.This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect.Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course

Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.

Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.


  • Inception of layout - CMOS fabrication process
    • Create active regions
    • Formation of N-well and P-well
    • Formation of gate terminal
    • Lightly doped drain (LDD) formation
    • Source drain formation
    • Local interconnect formation
    • Higher level metal formation
  • Introduction to ‘corner stitching’ and ‘tech files’
    • Corner stitch introduction
    • Corner stitch to planes to tiles
    • Active tile types and tech file content
    • Contact & styles
    • Connect section for circuit extraction
  • Design rule checking (DRC)
    • Introduction to DRC and lambda design rules
    • Poly extension and poly to diffusion spacing rules
    • Poly to diffusion spacing and diffusion contact width rules
    • Metal1 width and poly to metal1 spacing rules
    • Contact spacing and minimum active width rules
    • From logic to layout to SPICE
  • Introduction to euler's path and stick diagram
    • Introduction to simple path, euler's path and euler's circuit
    • Introduction to stick diagram
    • Derive actual dimension from stick diagram
  • Art of layout using Euler's path plus Stick diagram
    • Pre-layout simulation
    • Layout using 'only' stick diagram
    • Euler's path for Fn - Input gate ordering
    • Improved stick diagram for new gate input ordering
    • Abstract layout from stick diagram
    • Derive actual dimension for Fn
    • Script to create layout
    • Final layout and input/output labelling
  • Post-layout simulation and conclusion

Audience Profile

  • Anyone curious to know the inception of layout
  • Anyone curious to know the software behind layout drawing
  • Anyone who wants to know how chip designers talk with chip fabrication department


  • Basic terms of CMOS, NMOS, PMOS
  • A brief summary of my existing course on 'Circuit design and SPICE simulations' will help, but can do even without that course
  • A brief knowledge of my existing courses on physical design flow and static timing analysis will also help

Tools Used

Magic is a venerable VLSI layout tool, primarily for writing the scripting interpreter language Tcl.

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