# VSD - Circuit Design & SPICE Simulations - Part 1

### Overview

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis. OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more.These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.

And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst

So let's get started and keep those questions coming in the forum, and I will answer all of them.

### Objective

• Introduction to circuit design and SPICE simulations
• Why do we need circuit design and SPICE simulations?
• Introduction to basic element in circuit design - NMOS
• Strong inversion and threshold voltage
• Threshold voltage with positive substrate potential
• NMOS Resistive region and saturation region of operation

• Resistive region of operation with small drain-source voltage
• Drift current theory
• Drain current model for linear region of operation
• SPICE conclusion to resistive operation
• Pinch-off region condition
• Drain current model for saturation region of operation
• Introduction to SPICE

• Basic SPICE setup
• Circuit description in SPICE syntax
• Define technology parameters
• Standard technology file
• First SPICE Simulation
• SPICE deck for 1.2u Technology node
• SPICE simulation for lower nodes and velocity saturation effect
• SPICE simulation for lower nodes (250nm)
• SPICE deck for 250nm Technology node
• Drain current vs gate voltage for long and short channel device
• Id-Vgs SPICE deck for 1.2u technology node
• Id-Vgs SPICE deck for 250nm technology node
• Velocity variation at lower and higher electric fields
• Velocity saturation drain current model
• CMOS voltage transfer characteristics
• MOSFET as a switch
• Introduction to standard MOS voltage current parameters
• PMOS NMOS drain current v/s drain voltage
• Step1 - Convert PMOS gate-source-voltage to Vin
• Step2 & Step3 - Convert PMOS and NMOS drain-source-voltage to vout
• Step4 - Merge PMOS - NMOS load curves and plot VTC
• Quiz and Assignments on Threshold Voltage

### Audience Profile

• Anyone interested to know, what drives this \$Billion VLSI industry
• Anyone looking to do some practical and hands-on work on SPICE simulations.
• Any professional already doing Static Timing Analysis and wants to go into details of delay models
• Anyone looking to stay for a long time in VLSI domain

### Prerequisites

• Basic understanding on Industiral physical design flow, clock tree synthesis and static timing analysis to get applications of this course
• Even if you are not aware of above one's, that's even better, you can start from scratch

### Tools Used

"ngSpice" is open source a mixed-level/mixed-signal circuit simulator