VLSI – Essential concepts and detailed interview guide

VLSI - Essential concepts and detailed interview guide

Overview

This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.This course covers most topics in brief and not in detail, just to revise topics below interviews. For detailed and thorough discussion of each topic, you need to go to individual courses.

To bridge the gap between Understanding and Application of Knowledge, this leads to innovation

Objective

Physical Design Flow Overview
- Floor-Planning Steps
- Netlist Binding And Placement Optmization
- Clock Net Shielding
- Route - DRC Clean - Parasitics Extraction - Final STA
Floorplanning
- Utilization Factor And Aspect Ratio
- Concept of Pre-placed Cells
- Power Planning
- Pin Placement And Logical Cell Placement Blockage
Placement
- Netlist Binding And Placement
- Optimize Placement Using Estimated Wire Length And Capacitance
- Optimize Placement Continued
Timing Analysis With Ideal Clocks
- Setup Time Analysis And Introduction To Flip-Flop Setup Time
- Setup Timing Analysis With Multiple Clocks
- Multiple Clock Timing Analysis And Introduction To Data Slew Check
- Data Slew Check
Clock Tree Synthesis - Introduction And Quality Check Parameters
- Introduction To Clock Tree Synthesis
- Duty Cycle And Latency Check
- Latency And Power Check
- Power And Crosstalk Quality Check
- Glitch Quality Check
H-Tree
- H-Tree Algorithm And Skew Check
- H-Tree Pulse Width And Duty Cycle Check
- H-Tree Latency And Power Check
Clock Tree Modelling and Observations
- Clock Tree Modelling
- Clock Tree Building
- Clock Tree Observations
Buffered H-Tree
- H-Tree Buffering Observations
- H-Tree Pulse Width Check And Issues With Regular Buffers
- CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
- H-Tree Clock Buffers And Pulse Width Check
- Dynamic Power And Short Circuit Power
Clock Tree Optimization Checklist
- Optimization Checklist
- Leakage Current Reduction Technique
- Optimized Clock Tree Power And Latency Check
Static Timing Analysis With Real Clocks
- Static Timing Analysis With Real Clocks
- Impact Of Unbalanced Skew On Setup Time
- Impact Of Unbalanced Skew On Hold Time
Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP ??
- Dominant Lateral Capacitance
- Noise Margin Voltage Parameters
- Lower Supply Voltage
Glitch Examples And Factors Affecting Glitch Height
- Basic Crosstalk Glitch Example
- Glitch Discharge With High Drive Strength PMOS Transistor
- Factors Affecting Glitch Height - Aggressor Drive Strength
- Factors Affecting Glitch Height - Conclusion
Tolerable Glitch Heights and Introduction to AC Noise Margin
- Impacts Of Glitch
- Tolerable Glitch Heights Using DC Noise Margin
- AC Noise Margin
- Justification Of Load Impact And Conclusion
Crosstalk Delta Delay Analysis
- Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
- Setup Timing Analysis Using Real Clocks
- Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction
- Impact Of Crosstalk Delta Delay On Hold Timing
Noise Protection Technique
- Shielding
- Spacing
- Drive Strength
Routing And Design Rule Check (DRC)
- Introduction To Maze Routing - Lee's Algorithm
- Design Rule Check
Parasitics Extraction
- Introduction To IEEE 1481-1999 SPEF Format
- SPEF Header Description, Physical Design Flow Conclusion And What Next !!
Generated clocks definition and creation
- Define generated clock for Divide-by-2 circuit
- Generated clocks using master clock edges
- Generated Clock waveform derivation
- Generated clock with shifted edge
Basic of MOS Transistor
- Introduction to VLSI Academy
- Gate Voltage and accumulation of Negative Charge
- N-Channel formation between source and drain
- Impact of Substrate Potential of Threshold voltage (VT)
Setup & Hold timing Analysis
- Initial timing analysis and introduction to flop setup time
- Setup timing analysis with Jitter and real clocks
- Introduction to slack and hold timing analysis
- Hold timing analysis concluded