Verilog HDL Digital Design Workshop: From Fundamentals to Complex Circuits
This 5-day workshop provides a comprehensive overview of digital logic design using Verilog HDL. Participants will start with an introduction to digital design on Day 1, including datatypes and operators. They will then move on to Combinational Logic on Day 2, where they will learn about the basics of combinational logic design and how to use combinational logic gates to design circuits.
On Day 3, participants will learn about Sequential Design, which covers the basics of sequential logic design using Verilog HDL. This includes designing sequential circuits using flip-flops and implementing them in Verilog. Day 4 focuses on Complex Sequential Logic and State Machines, where participants will learn how to design complex sequential circuits such as counters, shift registers, and state machines using Verilog HDL.
Finally, on Day 5, participants will learn how to design and implement First-In-First-Out (FIFO) and Random Access Memory (RAM) using Verilog HDL. They will also learn how to design state machines to control the operation of these circuits. Throughout the workshop, participants will have the opportunity to apply what they have learned through hands-on lab exercises in Verilog HDL.
By the end of the workshop, participants will have gained a strong foundation in digital logic design using Verilog HDL. They will be able to design and implement a wide range of digital circuits, including combinational and sequential circuits, state machines, and memory circuits. The hands-on lab exercises will provide them with practical experience, enabling them to confidently apply their knowledge in real-world situations. Overall, this workshop provides a valuable learning opportunity for anyone interested in digital logic design using Verilog HDL.
Day1: Introduction, Datatypes & Operators
Theory:
- Introduction to Verilog Basics
- Verilog Design Styles: Dataflow, Behavioral, Structural
- Verilog Testbench
- Designing Combinational Logic with various operators
Labs:
- Getting started with edaplayground
- Designing and testing one bit half adder with Dataflow, Behavioral, and Structural Design in Verilog
- Designing and testing one bit full adder with Dataflow, Behavioral, and Structural Design in Verilog
- Verilog code to demonstrate the usage of all operators with $display or $monitor statements
- Create a Verilog function/task for Celsius to Fahrenheit conversion
Day 2: Combinational Logic
Theory
- 4-bit full adder design with testbench
- Multiplexer design: 2:1 and 4:1
- Encoder design: 2x4, 3x8, 4x2, and priority encoder
- 4-bit comparator design
- 8-bit barrel shifter (combinational left & right)
- Designing Arithmetic & Logic Unit (ALU)
Labs:
- Design and test 4-bit full adder with Dataflow in Verilog
- Design and test 2:1 Mux, 4:1 Mux, 2x4 Decoder, 4x2 Encoder, 4x2 Priority Encoder, 4-bit Comparator, 8-bit Barrel Shifter, and ALU in Verilog.
Day 3: Sequential Design
Theory
- Clock, D-Latch, and D-Flip Flop
- Types of D-Flip Flops and D-Latches, including asynchronous and synchronous reset versions
- Design of an 8-bit twin register set
Labs
- D-Latch with Asynchronous Reset
- D-Flip Flops with different types of reset and set signals
- Design of an 8-bit twin register set.
Day 4: Complex Sequential Logic and State Machines
Theory
- Shift Registers:
- Designing a 5-bit Left to Right Shift Register
- Designing a 5-bit Universal Shift Register
- Counters:
- Designing a basic counter
- Writing a Test Bench for a Counter
- Designing an Up Counter with Load Option
- Designing an Up or Down Counter
- Designing a Modulus Counter
- Designing a Range Up Counter
- Designing a Range Up or Down Counter with Load Option
- Clock Frequency Dividers:
- Designing a Clock Frequency Divider (Divide by 2)
- Designing a Clock Frequency Divider (Divide by 4)
- Designing a Clock Frequency Divider (Divide by 3) (Lab only)
Labs
- Shift Registers:
- Design a 5-bit Left to Right Shift Register in Verilog
- Design a 5-bit Universal Shift Register in Verilog
- Counters:
- Design a basic counter in Verilog
- Write a Test Bench for a Counter in Verilog
- Design an Up Counter with Load Option and Testbench in Verilog
- Design an Up or Down Counter with testbench in Verilog
- Design a Modulus Counter with testbench in Verilog
- Design a Range Up Counter with testbench in Verilog
- Design a Range Up or Down Counter with Load Option with testbench in Verilog
- Clock Frequency Dividers:
- Design a Clock Frequency Divider (Divide by 2) in Verilog
- Design a Clock Frequency Divider (Divide by 4) in Verilog
- Design a Clock Frequency Divider (Divide by 3) in Verilog (Lab only)
Day 5: FIFO, RAMS and State machines
Theory
- FIFOs:
- Designing a Single Clock First In First Out (FIFO)
- Designing a Dual Clock First In First Out (FIFO)
- Memory Arrays:
- Single Port Ram
- Dual Port Ram
- True Dual Port Ram
- State Machines:
- Mealy vs Moore Machine
- Mealy – 101 Non-Overlapping Sequence Detector
- Mealy – 101 Overlapping Sequence Detector
- Moore – 101 Non-Overlapping Sequence Detector
- Moore – 101 Overlapping Sequence Detector
- Miscellaneous topics
Labs
- FIFOs:
- Designing a Single Clock First In First Out (FIFO) in Verilog
- Designing a Dual Clock First In First Out (FIFO) in Verilog
- State Machines:
- Mealy – 101 Non-Overlapping Sequence Detector with testbench in Verilog
- Mealy – 101 Overlapping Sequence Detector with testbench in Verilog
- Moore – 101 Non-Overlapping Sequence Detector with testbench in Verilog
- Moore – 101 Overlapping Sequence Detector with testbench in Verilog
-
EDA Playground
- Virtual Coach platform with expert instructor guidance
- EDA Playground to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He has worked in design, development, and deployment of multiple static and constraints products.He is currently the Director of Product Strategy and Business Development at Real Intent.
At Real Intent, He is Driving Product Strategy for the Key Static Signoff Products. He is also working as an Advisor, Tech and VLSI Coach and Trainer for vlsideepdive in his spare time.
★ Seasoned Product Leader with multiple years of driving product strategy & product management
★ Highly effective product manager with strong customer focus
★ Tech and VLSI Coach & Trainer for hi-tech, product management, general management and growth hacking courses
★ Startup Advisor for multiple startups at pre-seed stage
★ Always pushing for innovation
★ Youtuber driving youtube channel of vlsideepdive
★ Speaker at multiple conferences and vlsideepdive events
★ Professional with over 17 years of technology management experience representing various stages of product life cycle including product development, product management, implementation management and product support
★ Extensive experience developing and validating positioning, messaging, competition, segmentation, and go-to-market strategy for a fast-paced, high growth technology market
★ Strong tech industry experience in understanding, development, and deployment of solutions for complex problems
Refund Policy: Last date to apply for refund is 10 April 2023 11:59 PM IST.
Refund Policy: If you are not able to join workshop, Last date to apply for refund is 10 April 2023 11:59 PM IST.
For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/
For Information drop email :vsd@vlsisystemdesign.com
Format: Cloud based Virtual Training Workshop
Duration - 5 Day
Registration Fees : $70 $30
Date : 12-16 April 2023 (Cancelled)
Registration: Registered participants Fees will be refunded soon.
For more Information : vsd@vlsisystemdesign.com
