A timing ECO should be power, performance and area aware and that was the crux of this webinar, where we discussed several strategies about how to do effective ECO as an expert .Slack based ECO is a beautiful strategy which helps you to achieve your timing target, while helping you to reduce on power and area
A PPA card like the above, is something which every VLSI engineer should be carrying like a business card. Why? Right from RTL to synthesis to PNR to signoff, we do things like upsize, downsize, VT swap, and many more, and all these factors impacts or tweaks your design PPA in one way or the other.
Let’s take an example of ‘downsize’