memories – VLSI System Design

5th mile-stone in field of open-source – another compact SRAM

This time its @Reuel did a pretty great job of building a pretty compact 6T-SRAM cell and he is just a third year engineering student

Let Knowledge Win

Trust me – KNOWLEDGE TRANSFER to students is MOST SATISFYING feeling.

The key thing over here – It must be short and crisp so everyone can enjoy the topic. These are memorable times, where everyone needs to do their bit to fight a battle against an unknown enemy. You need not make new slides, you are free to present your personal/company slides, provided it’s available on public platform.

Selective Non-Default Rules Based Clock Tree Synthesis using open-source EDA

Hey There – Think about it…!! Problem Statement – For hierarchical designs ~500k instance count, participants are expected to develop code which will modify existing […]

Default-Rules Based Clock Tree Synthesis in open-source EDA

For hierarchical designs ~500k instance count, participants are expected to develop code which will build clock tree for a design which has close to ~50k sequential flip-flops using default routing rules

How about pre-route and power-grid generation in opensource EDA?

Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]

Think about pre-placed cells and power ring generation in opensource EDA

Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]

Let’s re-think open-source EDA – core and die

Hey There – Think about it!!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]

Distributed timing analysis webinar

There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analysis across different machines.