Its a glimpse of physical design flow, static timing analysis, static circuit simulation, dynamic circuit simulations, leakage & switching power concepts, crosstalk glitch & delta delay concepts and basic delay of a cell.
Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I […]
Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I […]