Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – The energy, the keynotes, the presentations – they all were so perfect. VSD would like to thank all participants, keynote speakers and presenters from all […]Continue reading
Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.