Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
Design Verification is critical to proving functional correctness and establishing confidence in a design. Several studies from industry and academia, particularly over the course of the last two decades, have explored various verification methodologies that fall somewhere between dynamic or purely static formal approaches.
Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verification methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.