VIVO – A Popular CCS noise model to find delay change

Its static though, but really efficient….. I am referring to voltage-in-voltage-out VIVO model which is nothing but a current table as a function of input voltage level and output voltage level Here’s the setup to measure dc_current, a very popular pin-level group used for CCS noise modelling. This needs a […]

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Signal integrity (SI-glitch) – Part 3

Hello Hope you had a great weekend! I didn’t had one, as was busy preparing high quality videos on Circuit design and SPICE simulations, which will be my 5th official VLSI course on Udemy. Yayyyyy !! But why am I doing this….? I think, till now, after reading so many of my […]

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Signal integrity (SI-glitch) – Part 2

Hello First of all, I would like to ‘Thank You’ all for the messages/doubts that you have sent me over linkedin, vsd@vlsisystemdesign.com, facebook, etc. Really overwhelmed by the responses on my previous post. But not sure, whether you all know, we already have an online course on Signal Integrity, that’s a one-stop shop […]

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Signal integrity (SI-glitch) – Part 1

Hello Let me start this with a 30 sec video Well …. That’s glitch … Plain and simple !!! 🙂 Ahhh…. It’s a pain … right !! I can tell you exactly, why the above happens. Stay with me!! On a circuit, fabricated on silicon, there are trillions of wires packed […]

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