Aggressor – VLSI System Design

VIVO – A Popular CCS noise model to find delay change

Its static though, but really efficient….. I am referring to voltage-in-voltage-out VIVO model which is nothing but a current table as a function of input […]

Signal integrity (SI-glitch) – Part 3

Hello Hope you had a great weekend! I didn’t had one, as was busy preparing high quality videos on Circuit design and SPICE simulations, which will be […]

Signal integrity (SI-glitch) – Part 2

Hello First of all, I would like to ‘Thank You’ all for the messages/doubts that you have sent me over linkedin, vsd@vlsisystemdesign.com, facebook, etc. Really overwhelmed by the […]

Signal integrity (SI-glitch) – Part 1

Hello Let me start this with a 30 sec video Well …. That’s glitch … Plain and simple !!! 🙂 Ahhh…. It’s a pain … right […]