read_sdc – clock constraints

read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.

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First things first – Timing Graph – Part 2

Hello Now that we know what a timing graph is, let me unveil actual arrival time (AAT), required arrival time (RAT) and slack. We have seen these terms in a timing report, but what I will be talking about in this post is more from an algorithm viewpoint. Stay with […]

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First things first – Timing graph- part 1

Hello This is like the ‘Batman’ of static timing analysis. We have heard stories about it but never seen it. The reasons, this comes more from an algorithm point of view. How about looking a level higher and a level deeper into below timing path?​ I will take an example […]

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