VLIS SoC/Physical design using open-source EDA Tools

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

  • Students will be able to build and configure their own SoC (System-On Chip)
  • Students will be able to create their own defition of GPIO

  • Understand decision making process like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more

Workshop Day wise Content :

Day 1: To study various components of RISC-V microprocessor based SoC and review RISC-V picoSoC

  • Brief introduction RISC-V ISA and simulator. Run simple calculator ‘C’ code on a real processor written in Verilog
  • Overview of RISC-V based micro-processor and its related SoC
  • Overview of QFN48 package, pads, macros, analog components, and memory in open-source
  • Mixed-signal functionality simulation and Logic synthesis of above picoSoC verilog using open-
  • source Synthesis engine

Day 2: To understand importance of good vs bad floorplan and introduction to library cells using open- source tool

  • Pros and cons of good-bad floorplan
  • Idea of chip-planning, aspect ratio, utilization factor, power planning, decoupling capacitor,
  • pads/memory, and macro placement
  • Introduction to lab to create floorplan for small design, which will be covered in detail on Day 4)
  • Physical design overview
  • Why Libraries are called the soul and heart of semi-conductor industry?
  • Standard cells library overview

Day 3: To design and characterize one library cell using open-source Layout tool and spice simulator

  • Art of layout – Stick diagram + Euler’s path using open-source Layout tools
  • Characterization of important parameters (rise_time, rise_delay, fall_time, fall_delay) using
  • open-source SPICE tool
  • Introduction to 16-Mask CMOS fabrication process and its significance to chip design flow
  • High fanout net synthesis interactive tutorial using open-source synthesis too

Day 4: To do pre-layout static timing analysis and understand the importance of good clock tree

  • Introduction to static timing analysis and the related Industry standard reporting formats
  • Pre-layout timing analysis of a design using open-source STA tool, which includes setup timing
  • analysis for reg2reg and IO
  • Introduction to clock tree synthesis (CTS) and its related checks viz. skew, latency, pulse-width,
  • duty cycle
  • Placement/Routing/CTS of a design using open-source RTL2GDS tool
  • Perform CTS quality and routing quality checks using open-source STA\page1image35456128

Day 5: To understand full-chip integration steps and implement E31 RISCV design using open-source tool- chain

  • Full chip integration using open-source for a design with blocks and pads.
  • Revise floorplan from Day 2
  • Populate layout from library manager in open-source, select digital core block and additional
  • pads
  • Arrange pads and create a pad-frame hierarchy
  • Project work using SiFive E31 RISC-V design blocks

Audience Profile

  • Anyone who wants to learn SoC planning
  • Anyone who wants to learn chip design from specifications to Layout
  • Anyone curious to know, what happens before Synthesis, Physical design and STA

Prerequisites

  • Knowledge on RISC-V is nice to have, but not must to have
  • Digital design concepts and a bit of verilog syntax is nice to have

Format >> 

Cloud based Virtual Training Workshop

Duration >> 5 Days

Cost >>  $199

Stay tuned !!

For Information email: vsd@vlsisystemdesign.com