VLSI SoC/Physical design using open-source EDA Tools

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

  • Students will be able to build and configure their own SoC (System-On Chip)

  • Students will be able to create their own defition of GPIO

  • Understand decision making process like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more

Workshop Day wise Content :

Daywise Content

Topic to be covered

Day 1 
Study and Review various components of RISC-V based picoSoC

IC Design components terminologies

Let's talk to computers

RISC-V based SoC reference design

Get familiar to open-source EDA Tools

Day 2 
Chip planning strategies and introduction to foundry library cells

Chip Floor Planning considerations

Library Binding and Placement

Cell Design and Characterization flows

General timing characterization parameters

Day 3 
Pre-layout timing analysis and importance of goods clock tree

Labs for CMOS inverter ngspice simulations

Art of Layout using Euler's path plus stick diagram

Labs for Magic and post-layout ngspice simulations

Inception of Layout - CMOS fabrication process 

Day 4 
Pre-Layout timing analysis and importance of good clock tree

Timing modelling using delay tables

Timing analysis with ideal clocks

Clock tree synthesis and Signal Integrity

Timing Analysis with Real clocks

Day 5
Final steps for RTL2GDS

Routing and Design rule check (DRC)

Audience Profile

  • Anyone who wants to learn SoC planning
  • Anyone who wants to learn chip design from specifications to Layout
  • Anyone curious to know, what happens before Synthesis, Physical design and STA

Prerequisites

  • Knowledge on RISC-V is nice to have, but not must to have
  • Digital design concepts and a bit of verilog syntax is nice to have

Format : 

Cloud based Virtual Training Workshop

Duration : 5 Days

Cost :  $199 $70

Date :  3-7 March 2021

Last date for Registration: 2 March 2021

For Information email: vsd@vlsisystemdesign.com

Registration : CLOSED