VSDOpen 2020 Cloud Lab based Workshop

on VSD-IAT (Open 24 Hrs)

Open Source EDA Tool Development

Overview :

Familiarize with the resources available to open source EDA tool developers; how they can find out what are the development goals most urgently needed, how they can help with development, and how to keep tool chains cohesive and avoid fracturing the ecosystem into many incompatible parts. Exercises will involve finding smaller problems that can be solved mostly with scripting languages such a python and figuring out how to tackle them, how to contributed back to the project, and how to be noticed and appreciated.

Instructor

RISC-V Microarchitecture TL-Verilog

Overview :

Get a taste of next-generation, cloud-native design methodology using TL-Verilog and the Makerchip.com online IDE to design your very own RISC-V CPU hardware. Steve Hoover will guide you through the basics of digital logic with TL-Verilog. You’ll implement decode and execution logic for a simple RISC-V subset core, and you’ll see the inner workings of your CPU executing a simple test program.

Instructor

SoC Design using OpenLane

Overview :

Building a completely open-source System-on-Chip (SoC) means using open-source tools, an open-source Foundry Process Design Kit (PDK), and open-source IP libraries including standard cell libraries and analog blocks. Such an effort involves many challenges and requires careful attention to tons of details. In this workshop, we will guide you through the journey of physically implementing a small RISC-V based SoC, striVe, using OpenLANE ASIC flow targeting the recently released open-source SKY130 PDK.

Instructor

Registration for Workshop

Date

Workshop Title

Instructor 

Registration Fees

7th October 2020

Open Source EDA Tool Development

Tim Edwards

$5

8th October 2020

RISC-V Microarchitecture TL-Verilog

Steve Hoover

$5

9th October 2020

SoC Design using OpenLane

Mohammed Shalan

$5

7-9 October 2020

Register for all 3 Workshop

$15   $10

International Participant
Indian Participant