VSD-Hardware Design Program Annual Discount "Black Friday and Cyber Monday"
Overview :
10 Week Program Content
Introduction to the BabySoC
- What is SoC
- What is RISC-V CORE
- What is PLL
- What is DAC
BabySoC Modeling
- RISC-V CORE modelling
- PLL and DAC modelling
- Step-by-step modelling walkthrough
Post-synthesis simulation
- Synthesizing using Yosys
- How to synthesize the design
- Post-synthesis simulation (GLS)
- Yosys final report
- Static timing analysis using OpenSTA
BabySoC Physical Design and STA
- OPENLANE details and flow
- Floorplanning and Standard Cells
- Aspect Ratio and Utilization Factor
- Preplaced Cells
- Decoupling Capacitors
- Power Planning
- Pin Placement
- Floorplanning with OPENLANE
- Placement
- Viewing Placement in OPENLANE
- Standard Cell Design Flow
- Standard Cell Characterization
- Floorplanning and Standard Cells
- CTS and custom cell generation
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- Introduction to CTS Quality Checks
- H-Tree algorithm, skew check, pulse width, duty cycle, latency, and power check
- Buffered H-Tree, clock buffers vs regular buffers, dynamic, short-circuit and leakage power
- CTS for the uneven spread of clock endpoints
- Advanced H-Tree for million flop clock end-points with an uneven spread
- Clock gating technique using AND, OR Universal NAND gate
- Including Custom Cells in OPENLANE
- Fixing Slack Violations
- Viewing Post-CTS Netlist
- Post-CTS STA Analysis and impact of unbalanced skew on setup/hold time
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- RISC-V CORE RTL2GDSII flow
- RISC-V CORE layout generation setting up the environment
- RISC-V CORE layout generation flow configuration
- RISC-V CORE layout generation flow running
- RISC-V CORE post-routing STA
- RISC-V CORE post-routing simulation
- RISC-V CORE final GDSII layout
- BabySoC-a mixed-signal RTL2GDSII flow
- Prerequisites for mixed-signal implementation
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- LIB file and its usage
- LEF file and its usage
- ANALOG DAC-a digital to analogue converter
- ANALOG DAC getting the IP core
- ANALOG DAC preparing the LIB file
- ANALOG DAC preparing the GDS file
- ANALOG DAC preparing the LEF file
- ANALOG PLL-a phase-locked-loop
- ANALOG PLL Getting the IP core
- ANALOG PLL Preparing the LIB file
- ANALOG PLL Preparing the GDS file
- ANALOG PLL Preparing the LEF file
- BabySoC layout generation flow configuration
- Creating proper SDC file
- Floorplanning and placement configurations
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- Prerequisites for mixed-signal implementation
- BabySoC layout generation flow running
- BabySoC post-routing STA, SI and ECO
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- Basics of STA,
- Delays
- Timing Arcs
- Constraining the Design
- Constraining the Reg2Reg, Reg2IO, and IO2Reg Paths
- Input transition and Output Load and its effects on IO delays
- Clock Skew and Clock Jitter, its modelling in DC
- Writing SDCs
- Creating Clocks
- Specifying IO Dela
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Register Now
Program Date : 20 November 2022
Fees : $999 $450
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