Digital System Design and Modelling using Verilog

We thank Prof. V Kamakoti, IIT Madras for delivering Honorary Lectures in this workshop

Overview :

Verilog Hardware Description Language or Verilog-HDL has been widely used to model hardware since many years. From a specification to its hardware description, each phase of writing HDL code brings it’s own challenges and surprises. “So what exactly are these challenges?” “How can I describe a 32/64-bit ALU used in processors?” “Can I describe finite state machine is the most easiest way?” "Can I model PMOS/NMOS in verilog using primitives and simulate?" "Are MOS primitives synthesizable?"- If you have these questions and if you are eager to delve into the world of "Digital System Design and Modelling using Verilog". Wait no more!

This workshop is an OPPORTUNITY for all students across the globe, including VSD students, to learn from a Professor who has made our country India proud by releasing first ever Made In India RISC-V based processor Shakti. Don't miss this 1-day workshop on Digital System Design and modelling using Verilog. All the best

1-Day workshop with cloud based verilog labs

  1. Basics of transistors and logic gates (1hour)
    1. CMOS Transistor theory (PMOS/NMOS/MOS Layers)
    2. Tx gates, inverter,
    3. Logic switches (NAND/NOR gates)
    4. Simulation using MOS primitives and iverilog simulator
  1. Gate-level design and modelling (1hour 30min)
    1. Basic pos-level latch using CMOS Transistors
    2. Simulation of pos-level latch with blocks built using MOS primitives
    3. Structural representation of circuit and systems (eg. 32/64-bit adder)
    4. Parameterized simulation strategy of 32/64-bit adder
  1. Sequential Circuit design (1hour 30min)
    1. Design representation (block diagram, state diagram, timing diagram, circuit diagram, verilog)
    2. State machine lab to count even and odd number of zero’s and one’s for a system
      Simulation hick-ups in above state-machine and need for hand-shaking protocols (request-ack, ready-valid signals)

NOTE - At the end of workshop, a very well-structured GitHub link for all above labs will be shared with all participants to practice after the workshop


Refund Policy:

  1. Last date to apply for refund is 7 December 2020.
  2. Students absent during Workshop NOT eligible for Refund.


Cloud based Virtual Training Workshop

Registration  : Stay Tuned !!

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