Good Design Compiler is an Advanced Synthesis Tool used by leading semiconductor companies across world.
Synthesis of logic circuits plays a crucial role in optimizing the logic and achieving the targeted performance, area and power goals of an IC.
Understanding the fundamentals of design are very important to give the correct inputs to the tool to achieve the best-in-class netlist quality.
This workshop explores the following aspects,
- Design fundamentals
- Setting up DC for synthesis
- Understanding STA
- Understanding and writing the Synopsys Design Constraints [SDC].
- Analyzing the quality of netlist synthesized.
SDCs [Synopsys Design Constraints] are standardized way of constraining the design across the EDA [Electronic Design Automation] tools. Understanding the SDCs helps to work across the EDA implementation tools.