In this 8-week internship I spent the first week on researching existing work and making design decisions for the PLL components namely – Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator and Frequency Divider. I also looked into linking of the Sky130nm PDK with SPICE for the circuit implementation.
What I did in 8-weeks-VSD Internship? – Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
Semiconductor memories are an integral part of all systems to store large quantities of digital information. One of the important types of semiconductor memory is […]