Power aware clock tree synthesis – Part 4

Hello We were looking for a solution for below scenario, and you will be amazed to see, how an ‘Universal Gate’ solves the below problem (of-course, at the cost of increased area, but you save lot of power, which is a prime necessity¬†in your smartphones) The question is ‘How’? Let’s […]

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Power aware clock tree synthesis – Part 3

Hello And here’s the solution to the problem posted in my previous article. ‘AND gate itself’. If you observe carefully, you tie one of the inputs of an AND gate to ‘logic 1’ and it will behave like a buffer. Advantage …. I will show you soon. Disadvantage… Area overhead […]

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