Static Timing Analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
The workshop covers all the basic concepts in STA and Timing constraints. It starts with basics of Static Timing Analysis, timing paths, startpoint, endpoint and combinational logic definitions. It explains setup and hold checks, how STA tools calculate setup and hold violations. Then it slowly builds up to cover all aspects of STA like multiple types of timing paths, design rule checks, checks on async pins and clock gates. After that we go into slightly advanced topics like Time borrowing on latches, timing arcs, cell delays and models, impact of clock network on STA.
Since STA and timing constraints go hand in hand the workshop covers basics of all the timing constraints that an engineer should know for STA like clock definitions, clock groups, clock characteristics, port delays and timing exceptions.
Each day of the workshop is associated with labs so attendees can apply the concepts they have leant that day on practical examples and deepen their knowledge of the concepts.
Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He has worked in design, development, and deployment of multiple static and constraints products. He is currently the Director of Product Strategy and Business Development at Real Intent.
At Real Intent, he is Driving Product Strategy for the Key Static Signoff Products. He is also working as an Advisor, Tech and VLSI Coach and Trainer for vlsideepdive in his spare time.
★ Seasoned Product Leader with multiple years of driving product strategy & product management
★ Highly effective product manager with strong customer focus
★ Tech and VLSI Coach & Trainer for hi-tech, product management, general management and growth hacking courses
★ Startup Advisor for multiple startups at pre-seed stage
★ Always pushing for innovation
★ Youtuber driving youtube channel of vlsideepdive
★ Speaker at multiple conferences and vlsideepdive events
★ Professional with over 17 years of technology management experience representing various stages of product life cycle including product development, product management, implementation management and product support
★ Extensive experience developing and validating positioning, messaging, competition, segmentation, and go-to-market strategy for a fast-paced, high growth technology market
★ Strong tech industry experience in understanding, development, and deployment of solutions for complex problems
Participants should Know basics of setup and hold time, meaning of flops, gates latches, also have some idea about vlsi design flow
It's discounted to $30 ($99) as we want everyone to have access to Open-source EDA tools and PDK's for college projects, PhD, Semester Lectures and latest industry trends
Students who want to understand STA, and gain some experience in the field
Students/ young Professionals working in other fields of vlsi wanting to switch to this field
Experienced professionals wanting to brush up their skills, prepare for interviews or want to learn advanced concepts of STA
Professionals already working in STA/Physical design/backend wanting to upskill
Yes. The workshop is conducted on VSD-IAT cloud platform, which allows you to login at your convenient time within 24hrs from 18 May, 00:00hrs IST to 22 May, 11:59pm IST
We would suggest you to refrain from joining this workshop, as it's especially designed only for freshers looking to start in the field of VLSI. But, if you are looking to share your SoC and Physical Design experience with students, then you are more than welcome to join.
You will be given lifetime access to all lab files after the workshop. Access to videos and VSD-IAT platform will terminate on last day of Workshop
No. Labs will be done on VSD-IAT cloud platform. You will be given access to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts to install all tools on your laptops so you can do all experiments on your laptop and revise
If you are not able to join workshop, Last date to apply for refund is 8th May 2025 11:59 PM IST.
VSD has been conducting Hardware design programs for 3 years now and seen some amazing results, like great opensource IPs, amazing solutions for power analysis, innovations using Sky130 PDKs and close to 50+ silicon ready designs awaiting tape-outs. The reason for the success of HDP is the level of freedom which it allows for innovation.
VSD follows a strict 5-stage process, which is a typical practice in top semi-conductor design companies, thereby, providing an experience which is similar work working for a design company. That is the reason this program is recommended by some top industry professionals.
Fresher or recently graduated or experienced professionals looking to brush fundamentals.
Atleast BE/BTech/ME/MTech or equivalent.
VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.
Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.
At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.
We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.
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The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.
Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.
VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.
Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.
