X

Wanna Know how to build custom RISC-V core for Products!!

Register Now
Skip to content
VLSI System Design Logo

Open to Innovate

  • Home
  • Products
    • VSDSquadron
    • Courses
    • VSD-IAT
    • VSD-HDP
    • VSD-HDP Success Stories
    • VSD IP Specs
      • IP Specs
      • IP by Interns
    • VSD Tapeout
    • VSD Hackathon Series
    • VSD Library
    • Let Knowledge Win!!
  • Blogs
    • VSD latest Blogs
    • VSD (Initial phase)
    • VSD Video blog
  • VSDOpen
    • 2023
    • 2022
    • Collaboration Sponsor
    • 2021
    • 2020
    • 2019
    • 2018
  • About VSD
    • About us
    • Past Events
    • Upcoming Event…
    • Terms and Conditions
  • Explore

Tag Archives: pin constrains

Paper 4: Rapid Physical Implementation and Integration using eFabless platform

This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform [1]. The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider

Continue reading

Blogs

© Copyright 2017 VLSI System Design CorporationTerms and Conditions
A SiteOrigin Theme
Facebook
Twitter
YouTube
YouTube
LinkedIn