In deep sub-micron technology (i.e. <130nm) and below, the lateral capacitance between nets/wires on silicon, becomes much more dominant than the inter layer capacitance. Hence, there is a capacitive coupling between the nets, that can lead to logic failures and degradation of timing in VLSI circuits. Crosstalk is a phenomenon, by which a logic transmitted in vlsi circuit or a net/wire creates undesired effect on the neighboring circuit or nets/wires, due to capacitive coupling.

Refer to the diagram below to get a clear picture on the effect of coupling capacitance on functionality and timing of VLSI circuits.

# Crosstalk Noise due to Coupling Capacitance

The disturbance at ‘A’ can potentially cause a disturbance at ‘V’, because of the mutual coupling capacitance, and if the disturbance at ‘V’ crosses noise threshold of the receiving gate ‘R’, then it may change the logic at the output of ‘R’ i.e., output of ‘R’, which is supposed to be at logic ‘1’, might switch to logic ‘0’, as it senses a logic ‘1’ at its input, due to the noise induced on its input by the disturbance at ‘A’.

Refer to diagram below to understand noise-induced bump characteristics at different noise margin levels.

If the bump height at victim ‘V’ lies between NMl (Noise Margin low), then the logic at victim ‘V’ will remain at logic ‘0’.

If the bump height at victim ‘V’ lies between V_{il} and V_{ih}, then the logic at victim ‘V’ is undefined, i.e. it might switch to logic ‘1’ or logic ‘0’.

If the bump height at victim ‘V’ lies between NMh (Noise Margin high), then the logic at victim ‘V’ will switch to logic ‘1’, leading to logic failures.

# Timing Degradation due to Coupling Capacitance

Consider input of driver ‘D’ switching from logic ‘0’ to logic ‘1’,thus the logic at node ‘V’ switches from ‘1’ to ‘0’. Now, if both ‘A’ and ‘V’ nodes have signal switching event at the same time interval, then, due to noise induced by signal transition at aggressor ‘A’, a change in the timing instant of the signal transition occurs at ‘V’, as shown in above figure. Due to this, the propagation delay of the driver ‘D’ increases by ‘dt’ amount of time, thus increasing the overall propagation delay of the circuit, which might lead to potential setup violation.

# Crosstalk Modelling and Analysis

Refer diagram below to understand the basic model of crosstalk

‘Victim’ and ‘aggressors’ drivers can be modeled by resistors ‘R_{V}‘ and ‘R_{A}‘, respectively. Whereas ‘victim’ and ‘aggressors’ loads can be modeled by capacitors ‘C_{V}‘ and ‘C_{A}‘, respectively. Let the coupling capacitance between them be C_{C}. The above model can be further simplified as shown in figure below.

In the above figure, t_{r} is the rise time at the aggressor node ‘A’, which is related to the gate delay R_{A} as shown in below equation:

t_{r} = R_{A} * ( C_{C} + C_{A} )

Essentially, the above figure represents a voltage source connected at aggressor node ‘A’ with a series capacitance ‘C_{C}‘. By Thevinin to Norton conversion, this voltage source can be replaced by a current source with parallel capacitance ‘C_{C}‘ as shown below:

We need to find the voltage equation at victim ‘V’, considering the final value of voltage as V_{final} shown in equation below:

V_{final} = I * R

V_{final} = (C_{C} / t_{r}) * R_{V}

The noise induced bump is nothing but charging-discharging waveform across capacitor as shown below:

The charging voltage across capacitor can be deduced from the following equation:

V_{charge} = V_{final} (1 – e^{-t/RC})

At t = t_{r}

V_{charge} = V_{p}

R = R_{V}, C = C_{C} + C_{V}

R_{V} * (C_{C} + C_{V}) = Equivalent Time Constant

V_{p} = (C_{C} / t_{r}) * R_{V} (1 – e ^{-tr /(RV *(CC + CV)}))

The figure below shows how peak voltage is a function of coupling capacitance C_{C}, Victime drive strength R_{V} and rise time on aggressor line.

The higher V_{p} is, there are more chances that it would exceed noise margin. But, that is not the only thing.

Consider a case, where the pulse height V_{p} is high (1V), with small pulse width (e.g. 1ps) as opposed to another scenario, where the pulse height is low (e.g. 0.3V) and pulse width is large (e.g. 100ps). This can be illustrated in the diagram below.

If the receiving gate’s RC delay is not in sync with the incoming pulse, it may not even recognize the incoming pulse (1V, 1ps). Therefore, even if the peak of the pulse is substantial, but pulse is narrower, its possible that the receiving gate doesn’t identify the existence of that pulse and it gets filtered out.

Therefore, we have 2 things to control

**1) Peak Voltage (V _{p})**

If x is very very small i.e. R_{v}(C_{C} + C_{V}) is large compared to t_{r}, then e^{-x} ~ (1 – X)

Therefore, V_{p} can be deduced as shown below:

Hence, the first solution to reduce crosstalk noise, is to increase the Resistance of Victim driver (R_{V}).i.e. downsize the victim driver, so that, the high resistance of the victim driver restricts the supply of current and charging of victim net capacitance during the rise time (t_{r}) of aggressor signal, which would in turn reduce the bump height.

The second solution to reduce crosstalk noise, is to increase the Capacitance of Victim load (C_{V}).i.e. upsize the victim load, thus the resistance will reduce, which will in turn help the victim net to maintain a strong static voltage.

**2) Pulse Width**

Pulse width, depends upon the aggressor net transition. The steep the transition is, on aggressor, the shorter will be the pulse width. This can be illustrated as shown in below diagram.

Hence, the third solution to reduce crosstalk noise, is to maintain sharp transitions on aggressor.

Another method to reduce crosstalk noise is to introduce shields in between victim and aggressor.