Hey, its time you take charge of your design!!

….And this is something which I can show you using the newly launched open-source EDA tool “eSim (FOSSEE IITB Project)”. Let’s assume for a moment, you do not have timing libraries, maybe because foundry doesn’t provide them (which is perfectly OK in terms of their business model) or maybe you […]

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Power aware clock tree synthesis – Part 4

Hello We were looking for a solution for below scenario, and you will be amazed to see, how an ‘Universal Gate’ solves the below problem (of-course, at the cost of increased area, but you save lot of power, which is a prime necessity in your smartphones) The question is ‘How’? Let’s […]

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Power aware clock tree synthesis – Part 3

Hello And here’s the solution to the problem posted in my previous article. ‘AND gate itself’. If you observe carefully, you tie one of the inputs of an AND gate to ‘logic 1’ and it will behave like a buffer. Advantage …. I will show you soon. Disadvantage… Area overhead […]

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Power aware clock tree synthesis – Part 2

Hello While trying to build a clock tree which is power aware, let’s go back a step ahead and look, what are the top observations for a clock network, and below image covers the same. Assuming a slew of ’40ps’ for the first buffer and capacitance of 60fF on node […]

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