SoC Labs - VLSI System Design

RISC‑V Reference SoC Tapeout Program

From Design to Silicon with Industry-Grade Tools

Emphasizes hands-on learning and end-to-end chip development

Overview

This project delivers a complete, hands-on journey to design, implement, and fabricate a RISC-V System-on-Chip (SoC) using Synopsys EDA tools and the SCL180 PDK. It’s crafted for students, educators, and professionals aiming to master end-to-end chip development—from RTL design to post-silicon validation. The RISC‑V Reference SoC Tapeout Program is a national-level initiative to empower engineering students with the most authentic VLSI experience—right from RTL design to actual silicon fabrication (tapeout). This program is part of India’s Semiconductor Mission to create skilled silicon designers who don’t just simulate—but fabricate. It brings together students, academic institutions, and national foundries to drive the next wave of innovation in VLSI.

Program Vision
Create a scalable and replicable reference tapeout program that can serve as a national framework for colleges and universities across India. This initiative focuses on building a proven, reusable methodology—from design to silicon—that academic institutions can adopt to execute their own production‑grade RISC‑V Reference SoC Tapeout Program using industry‑standard tools and PDKs.

Program Description
This 20‑week program demonstrates a complete tapeout cycle for a RISC‑V Reference SoC using Synopsys tools and the SCL180 nm PDK. It establishes an end‑to‑end flow—from RTL to GDSII and post‑silicon validation—combining online training with physical execution at IIT Gandhinagar (IITGN). The outcome is a reusable, documented flow that sets the standard for academic silicon tapeouts in India.

Project Highlights

Repository Setup & Functional Validation
Custom IP Integration
Full-Chip Gate-Level Simulation
Physical Design Preparation
Full-Chip Implementation
Signoff & Tapeout
Post-Silicon Validation

Schedule

Recruitment & Training (10‑Week Plan - Online)

Week	Dates	Theme	Hands‑on Labs (tool‑only)	Deliverables / Checkpoints
1	Thu, 18 Sep 2025 – Wed, 24 Sep 2025	Environment + RTL sim basics	Set up toolchain; run iverilog simulations; inspect signals in GTKWave; inject a small RTL bug and detect via sim	iverilog run logs; 2 annotated GTKWave screenshots; 5–7 lines on the bug & fix
2	Thu, 25 Sep 2025 – Wed, 01 Oct 2025	Synthesis & GLS	Synthesize with Yosys; Gate‑level simulation (GLS) with std‑cell models; compare RTL vs GLS behavior	Pre/post‑synth sim match screenshots; Yosys stat area/cell snippet; note on an observed optimization
3	Thu, 02 Oct 2025 – Wed, 08 Oct 2025	RISC‑V ISA & toolchain	Build & run a small RISC‑V program (riscv‑gnu‑toolchain); simulate CPU testbench with iverilog + GTKWave (fetch/decode)	Waves showing PC, instruction, decode outputs; brief note on pipeline stage boundaries
4	Thu, 09 Oct 2025 – Wed, 15 Oct 2025	Pipeline bugs, clock gating & CPU GLS	Reproduce a load‑use hazard; apply clock‑gating variant; re‑synthesize (Yosys); CPU‑level GLS with cell models	Waveforms: buggy vs fixed; one slide on toggle reduction with clock gating; GLS pass log snippet
5	Thu, 16 Oct 2025 – Wed, 22 Oct 2025	STA fundamentals	Write core timing constraints (SDC); run OpenSTA on post‑synth netlist; identify worst setup/hold paths & constraint gaps	Setup/Hold report excerpts (WNS/TNS); 5–8 lines justifying clocks/IO delays/false or multicycle paths
6	Thu, 23 Oct 2025 – Wed, 29 Oct 2025	CMOS & SPICE with SKY130	Draw basic gates in Xschem; simulate in ngspice; sweep VDD/Temp/Load; extract rise/fall delays	3 plots (delay vs load; delay vs VDD; rise vs fall); one‑pager explaining PVT effects on delay
7	Thu, 30 Oct 2025 – Wed, 05 Nov 2025	OpenLane: floorplan → placement	Run OpenLane through floorplan & placement; tune utilization/aspect; tap/decap insertion; check congestion metrics	Floorplan/placement metrics snapshot; congestion heatmap/metrics; note on best util/aspect found
8	Thu, 06 Nov 2025 – Wed, 12 Nov 2025	CTS, routing & post‑route STA	OpenLane: CTS → global/detail route; OpenSTA post‑CTS & post‑route; review hold fixes	Post‑route timing summary (WNS, TNS) at TT; final routed layout screenshot; note on hold‑fix strategy
9	Thu, 13 Nov 2025 – Wed, 19 Nov 2025	Multi‑corner timing + sign‑off	Multi‑corner OpenSTA (slow/typ/fast); generate SDF and run SDF‑annotated GLS; assemble sign‑off artifacts	Table of WNS/TNS across corners; SDF‑GLS pass log & wave snapshot; list of sign‑off artifacts
10	Thu, 20 Nov 2025 – Wed, 26 Nov 2025	Final polish & documentation	Re‑run best config to clean violations; summarize RTL→GDS flow, constraints, corner timing; short walkthrough video	Final timing & DRC status summary; 4–6 page PDF report; 2–3 min demo video link

Project Initialization @ IIT Gandhinagar (4‑Week Plan — Top 50)

Week	Dates	Theme	Hands‑on Labs (tool‑only)	Deliverables / Checkpoints
1	Wed, 10 Dec 2025 – Tue, 16 Dec 2025	Fix SDC & make Housekeeping synthesizable	Repair SDC header/vars; place read_sdc before compile; add create_clock, set_clock_groups -asynchronous, IO delays; set_false_path & set_disable_timing for ring‑osc/analog arcs; de‑tri‑state internals; guard SIM‑only code; synthesize Housekeeping standalone then top	Clean vsdcaravel.sdc; updated Housekeeping RTL (no internal Zs); DC reports (clocks/QoR/timing); post‑synth netlists (HK + Top)
2	Wed, 17 Dec 2025 – Tue, 23 Dec 2025	POR & SRAM macro plan + Hybrid GLS	Thin SCL POR/SRAM wrappers with USE_POWER_PINS; link macro .db/.lib in DC; mark dont_touch; provide SIM models; Hybrid GLS (GL for most; RTL for HK if needed); extend DV (UART, GPIO dir, Wishbone R/W, reset robustness); generate VCD/SAIF from RTL; rerun DC power with SAIF	POR/SRAM wrappers; updated DC link library & dont_touch; hybrid GLS script & passing logs; SAIF/VCD artifacts & updated power report
3	Wed, 24 Dec 2025 – Tue, 30 Dec 2025	Full GLS (no black‑boxes) + STA convergence	Replace HK RTL with synthesized netlist; include SDF as available; integrate SRAM/POR models in GLS; cut non‑digital arcs in STA; firmware smoke (mgmt core fetch, minimal CSR poke); tighten SDC (generated clocks, strap case‑analysis, IO loads); fix top violators; iterate simple ECOs	Full‑GLS waves + pass logs (HK, UART, GPIO, WB, boot); updated SDC; timing reports (top 100 paths) per iteration
4	Wed, 31 Dec 2025 – Tue, 06 Jan 2026	Sign‑off‑style STA & Handover	Final STA (setup/hold across corners; CDC review); final power with SAIF; DRC hygiene; reproducibility (make synth/gls/sta with docs)	STA pack (SDC + timing/power reports); GLS pack (scripts, pass logs, SDF list); Repro README + Make/Tcl entrypoints; closure slides

Inputs to Lock by 17 January 2026
PDK revision (SCL 180 nm) + layer map, DRC/LVS/antenna/density decks
IO library (2.5V) with ESD clamps & corner pads; core std‑cells (1.8V)
SRAM & POR macros: LEF/Lib/GDS/Verilog models (final names/versions)
Target corners: (TT/SS/FF) × (min/max V/T); recommended DFM rules from SCL

Final GDSII & Tapeout (6‑Week Plan — Synopsys + SCL180, Top 20)

Week	Dates	Theme	Hands‑on Labs (tool‑only)	Deliverables / Checkpoints
1	Sat, 17 Jan 2026 – Fri, 23 Jan 2026	PnR bring‑up, floorplan & pads	Freeze pad ring with SCL IO (ESD/corners/VDD/VSS); seal‑ring/scribe; floorplan (die/core, 55–65% util); place macros + halos; multi‑rail audit; level shifters if needed; PG grid; import clean SDC from GLS	Floorplan DEF/FP; pad ring + seal ring; PDN Tcl & tap/decap recipe; pinout CSV (bond map draft)
2	Sat, 24 Jan 2026 – Fri, 30 Jan 2026	Placement & pre‑CTS timing	Insert tie/spare cells; global placement & legalization; clock plan (roots, skew target, buffer list); pre‑CTS opt: fix max tran/cap/fanout; pipeline/resize if needed; early RC (global route) for realistic timing	Placed DEF; pre‑CTS timing (max/min); congestion & utilization reports
3	Sat, 31 Jan 2026 – Fri, 06 Feb 2026	CTS, post‑CTS timing & SI	Run CTS (balanced/useful skew); post‑CTS hold fixing; RC‑aware re‑opt (size/buffer); crosstalk mitigation; STA across TT/SS/FF	Post‑CTS DEF; timing (setup/hold, clock summary); clock QoR (insertion, skew, buffer count)
4	Sat, 07 Feb 2026 – Fri, 13 Feb 2026	Route, antenna, fill, draft DRC/LVS	Global + detailed route; antenna check/fix (diodes/jumps) & ECO route; metal density fill/slotting; first full‑chip DRC; prep LVS	Routed DEF/GDS; antenna & density reports; first DRC/LVS logs
5	Sat, 14 Feb 2026 – Fri, 20 Feb 2026	Sign‑off PEX, STA, IR/EM, GLS/FEV	Golden PEX → SPEF; sign‑off STA (all PVT + OCV/AOCV) & ECO; IR/EM; reinforce PG if needed; post‑layout GLS with SDF; formal equivalence	SPEF/SDF; sign‑off STA pack; IR/EM reports; GLS pass logs; FEV clean report
6	Sat, 21 Feb 2026 – Fri, 27 Feb 2026	Tapeout kit & submission	Final DRC/LVS = 0 (or approved waivers); re‑fill after ECOs and re‑DRC; build tapeout package (GDSII, layer map, tech notes, netlist, LEF, reports, waivers); SCL jobdeck/forms; top‑cell checks; bonding/package kit & pinout CSV; golden re‑runs	Submission archive (GDSII + docs) & checklist; bonding/package kit

Tools & Infrastructure

Training Stack: iverilog, GTKWave, Yosys, OpenSTA, Xschem, ngspice, OpenLane
Sign‑off Stack: Synopsys (Design Compiler, PrimeTime, ICC2/Fusion), foundry DRC/LVS decks
PDK: SCL 180 nm (IO 2.5V, Core 1.8V), SRAM/POR macros
Collaboration: Git/GitHub for version control; reproducible Make/Tcl entrypoints

Delivery & Locations

Recruitment & Training is delivered online with hands‑on labs. Project Initialization (Top 50) runs on‑site at IIT Gandhinagar. Final GDSII & Tapeout (Top 20) is executed with Synopsys tools and SCL180 inputs under an industry‑style sign‑off regimen.
Project Initialization (Top 50) runs on‑site at IIT Gandhinagar.
Final GDSII & Tapeout (Top 20) is executed with Synopsys tools and SCL180 inputs under an industry‑style sign‑off regimen.

Eligibility & Prerequisites

Program Outcomes

Deliverables for Participants

Why Join This Project?

How to Join?

Implicit Alignment with National Goals

Supported By: Semiconductor Laboratory (SCL), Synopsys, VLSI System Design.
Contact: [email protected]
This structured, hands-on journey equips participants with industry-relevant skills while fostering innovation in strategic sectors. Let’s tape out!
Travel & Accommodation
1) Travel and Food for top 50 candidates: self-funded by candidates
2) Hostel Accommodation for Top 50 candidates for 3 Weeks- 10 Dec 25 - 1 Jan 2026
3) Hostel Accommodation for Top 20 Candidates for 6 Weeks- 18 Jan - 27 Feb 2026

About VSD

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.