RISC-V based MYTH (Microprocessor for You in Thirty Hours)
A beginner level 5-day workshop on “RISC-V based MYTH” (24hrs x 5days on VSD-IAT platform)
When we say, “beginner level”, by end of workshop you will understand
• RISC-V specs
• RISC-V software
• How to implement RISC-V basic specs using TL-Verilog
• Simulate your own RISC-V core
*In short, you are going to write RTL and build RISC-V core on your own*
Workshop Day wise Content :
Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain
- Introduction to RISC-V basic keywords
- Labwork for RISC-V software toolchain
- Integer number representation
- Signed and unsigned arithmetic operations
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using Makerchip
- Sequential and pipelined logic
- Validity
- Hierarchy
Day 4: Basic RISC-V CPU micro-architecture
- Microarchitecture and testbench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Day 5: Complete Pipelined RISC-V CPU micro-architecture/store
- Pipelining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future opportunities
Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.
- RISC-V ISA Simulator
- RISC-V GNU Tool-chain
- Spike
- TL-Verilog
- Markerchip IDE
- Virtual Coach platform with expert instructor guidance
- Cloud-based dedicated Virtual Machine to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
- Simulate basic C program using RISC-V ISA simulator, debug using Spike - all on VSD-IAT platform
- Design own RISC-V core using TL-Verilog and verify using verilator - all on Makerchip IDE
Instructor Profile:
Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques
Steve Hoover, founder of Redwood EDA, Steve is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), available to all at makerchip.com. He is also the lead developer of the 1st CLaaS open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.
TA Profile:
Shivani Shah is currently a research student at the International Institute of Information Technology (IIITB), Bangalore. She was a participant in RISC-V MYTH Workshop by VSD and Redwood EDA in the second iteration. From the third workshop onwards, she is TA for this workshop.
Can I participate on my schedule in my timezone?
Yes, also you will be provided roughly 24x7 live support from mentors in various time zones over the duration of the workshop. We use Slack for live chat support and do also take up daily sync-up and one-to-one calls, as necessary.
Can experienced system designers join for refreshing concepts?
We welcome interested participants from all stages of their career. Even if you have learned logic design and CPU microarchitecture in the past, this course offers a modern perspective. TL-Verilog is a new and emerging standard and is useful for industry and academia alike. Get involved in revolutionizing your design/teaching/learning process!
I’m new to digital logic. Will I be able to complete the course?
This course teaches the basics of digital logic in the context of a modern design approach. So newcomers will learn something just as well as experienced designers. We have received positive feedback from learners ranging from 12 years of age to industry veterans, though we suggest this course for college age and above for folks on a technical path.
Can I access content after Workshop is finished ?
The main tool used in the workshop is the Makerchip.com online IDE, which is public and always open for development of open-source designs. You will also be given lifetime access to the slides and lab files after the workshop.
Do I need to install any software or tools to do labs?
No. Labs will be done on VSD-IAT cloud platform and Makerchip.com online IDE. You will be given access in your browser to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts and templates to install or use the tools on your personal systems.
How is TL-Verilog different from Verilog?
TL-Verilog (Transaction-Level Verilog) is a new and emerging standard supporting “timing abstract” digital design, without which this course would not be possible. In addition to its powerful modeling constructs, it also eliminates legacy complexities of Verilog such as regs and wires, generate blocks, blocking vs. non blocking etc. It provides clean semantics that are easy to learn whether you already know Verilog or not. It integrates with existing commercial and open-source EDA tools by generating synthesizable (System)Verilog. Learn more at https://www.redwoodeda.com/tl-verilog
Please check out the: https://www.vlsisystemdesign.com/hdp/
Refund Policy: If you are not able to join workshop, last date to apply for refund in 19 Sept 2023, 11:59 PM IST
For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/
