RISC‑V Reference SoC Tapeout Program

From Design to Silicon with Industry-Grade Tools

  • 20 Weeks
  • 20+ IPs
  • 100% Tapeout

Emphasizes hands-on learning and end-to-end chip development

Overview

This project delivers a complete, hands-on journey to design, implement, and fabricate a RISC-V System-on-Chip (SoC) using Synopsys EDA tools and the SCL180 PDK. It’s crafted for students, educators, and professionals aiming to master end-to-end chip development—from RTL design to post-silicon validation. The RISC‑V Reference SoC Tapeout Program is a national-level initiative to empower engineering students with the most authentic VLSI experience—right from RTL design to actual silicon fabrication (tapeout). This program is part of India’s Semiconductor Mission to create skilled silicon designers who don’t just simulate—but fabricate. It brings together students, academic institutions, and national foundries to drive the next wave of innovation in VLSI.

Program Vision
Create a scalable and replicable reference tapeout program that can serve as a national framework for colleges and universities across India. This initiative focuses on building a proven, reusable methodology—from design to silicon—that academic institutions can adopt to execute their own production‑grade RISC‑V Reference SoC Tapeout Program using industry‑standard tools and PDKs.

Program Description
This 20‑week program demonstrates a complete tapeout cycle for a RISC‑V Reference SoC using Synopsys tools and the SCL180 nm PDK. It establishes an end‑to‑end flow—from RTL to GDSII and post‑silicon validation—combining online training with physical execution at IIT Gandhinagar (IITGN). The outcome is a reusable, documented flow that sets the standard for academic silicon tapeouts in India.

Project Highlights

  • Repository Setup & Functional Validation
  • Custom IP Integration
  • Full-Chip Gate-Level Simulation
  • Physical Design Preparation
  • Full-Chip Implementation
  • Signoff & Tapeout
  • Post-Silicon Validation

Schedule

Recruitment & Training (10‑Week Plan - Online)

WeekDatesThemeHands‑on Labs (tool‑only)Deliverables / Checkpoints
1Thu, 18 Sep 2025 – Wed, 24 Sep 2025Environment + RTL sim basicsSet up toolchain; run iverilog simulations; inspect signals in GTKWave; inject a small RTL bug and detect via simiverilog run logs; 2 annotated GTKWave screenshots; 5–7 lines on the bug & fix
2Thu, 25 Sep 2025 – Wed, 01 Oct 2025Synthesis & GLSSynthesize with Yosys; Gate‑level simulation (GLS) with std‑cell models; compare RTL vs GLS behaviorPre/post‑synth sim match screenshots; Yosys stat area/cell snippet; note on an observed optimization
3Thu, 02 Oct 2025 – Wed, 08 Oct 2025RISC‑V ISA & toolchainBuild & run a small RISC‑V program (riscv‑gnu‑toolchain); simulate CPU testbench with iverilog + GTKWave (fetch/decode)Waves showing PC, instruction, decode outputs; brief note on pipeline stage boundaries
4Thu, 09 Oct 2025 – Wed, 15 Oct 2025Pipeline bugs, clock gating & CPU GLSReproduce a load‑use hazard; apply clock‑gating variant; re‑synthesize (Yosys); CPU‑level GLS with cell modelsWaveforms: buggy vs fixed; one slide on toggle reduction with clock gating; GLS pass log snippet
5Thu, 16 Oct 2025 – Wed, 22 Oct 2025STA fundamentalsWrite core timing constraints (SDC); run OpenSTA on post‑synth netlist; identify worst setup/hold paths & constraint gapsSetup/Hold report excerpts (WNS/TNS); 5–8 lines justifying clocks/IO delays/false or multicycle paths
6Thu, 23 Oct 2025 – Wed, 29 Oct 2025CMOS & SPICE with SKY130Draw basic gates in Xschem; simulate in ngspice; sweep VDD/Temp/Load; extract rise/fall delays3 plots (delay vs load; delay vs VDD; rise vs fall); one‑pager explaining PVT effects on delay
7Thu, 30 Oct 2025 – Wed, 05 Nov 2025OpenLane: floorplan → placementRun OpenLane through floorplan & placement; tune utilization/aspect; tap/decap insertion; check congestion metricsFloorplan/placement metrics snapshot; congestion heatmap/metrics; note on best util/aspect found
8Thu, 06 Nov 2025 – Wed, 12 Nov 2025CTS, routing & post‑route STAOpenLane: CTS → global/detail route; OpenSTA post‑CTS & post‑route; review hold fixesPost‑route timing summary (WNS, TNS) at TT; final routed layout screenshot; note on hold‑fix strategy
9Thu, 13 Nov 2025 – Wed, 19 Nov 2025Multi‑corner timing + sign‑offMulti‑corner OpenSTA (slow/typ/fast); generate SDF and run SDF‑annotated GLS; assemble sign‑off artifactsTable of WNS/TNS across corners; SDF‑GLS pass log & wave snapshot; list of sign‑off artifacts
10Thu, 20 Nov 2025 – Wed, 26 Nov 2025Final polish & documentationRe‑run best config to clean violations; summarize RTL→GDS flow, constraints, corner timing; short walkthrough videoFinal timing & DRC status summary; 4–6 page PDF report; 2–3 min demo video link

Project Initialization @ IIT Gandhinagar (4‑Week Plan — Top 50)

WeekDatesThemeHands‑on Labs (tool‑only)Deliverables / Checkpoints
1Wed, 10 Dec 2025 – Tue, 16 Dec 2025Fix SDC & make Housekeeping synthesizableRepair SDC header/vars; place read_sdc before compile; add create_clock, set_clock_groups -asynchronous, IO delays; set_false_path & set_disable_timing for ring‑osc/analog arcs; de‑tri‑state internals; guard SIM‑only code; synthesize Housekeeping standalone then topClean vsdcaravel.sdc; updated Housekeeping RTL (no internal Zs); DC reports (clocks/QoR/timing); post‑synth netlists (HK + Top)
2Wed, 17 Dec 2025 – Tue, 23 Dec 2025POR & SRAM macro plan + Hybrid GLSThin SCL POR/SRAM wrappers with USE_POWER_PINS; link macro .db/.lib in DC; mark dont_touch; provide SIM models; Hybrid GLS (GL for most; RTL for HK if needed); extend DV (UART, GPIO dir, Wishbone R/W, reset robustness); generate VCD/SAIF from RTL; rerun DC power with SAIFPOR/SRAM wrappers; updated DC link library & dont_touch; hybrid GLS script & passing logs; SAIF/VCD artifacts & updated power report
3Wed, 24 Dec 2025 – Tue, 30 Dec 2025Full GLS (no black‑boxes) + STA convergenceReplace HK RTL with synthesized netlist; include SDF as available; integrate SRAM/POR models in GLS; cut non‑digital arcs in STA; firmware smoke (mgmt core fetch, minimal CSR poke); tighten SDC (generated clocks, strap case‑analysis, IO loads); fix top violators; iterate simple ECOsFull‑GLS waves + pass logs (HK, UART, GPIO, WB, boot); updated SDC; timing reports (top 100 paths) per iteration
4Wed, 31 Dec 2025 – Tue, 06 Jan 2026Sign‑off‑style STA & HandoverFinal STA (setup/hold across corners; CDC review); final power with SAIF; DRC hygiene; reproducibility (make synth/gls/sta with docs)STA pack (SDC + timing/power reports); GLS pack (scripts, pass logs, SDF list); Repro README + Make/Tcl entrypoints; closure slides
  • Inputs to Lock by 17 January 2026
  • PDK revision (SCL 180 nm) + layer map, DRC/LVS/antenna/density decks
  • IO library (2.5V) with ESD clamps & corner pads; core std‑cells (1.8V)
  • SRAM & POR macros: LEF/Lib/GDS/Verilog models (final names/versions)
  • Target corners: (TT/SS/FF) × (min/max V/T); recommended DFM rules from SCL

Final GDSII & Tapeout (6‑Week Plan — Synopsys + SCL180, Top 20)

WeekDatesThemeHands‑on Labs (tool‑only)Deliverables / Checkpoints
1Sat, 17 Jan 2026 – Fri, 23 Jan 2026PnR bring‑up, floorplan & padsFreeze pad ring with SCL IO (ESD/corners/VDD/VSS); seal‑ring/scribe; floorplan (die/core, 55–65% util); place macros + halos; multi‑rail audit; level shifters if needed; PG grid; import clean SDC from GLSFloorplan DEF/FP; pad ring + seal ring; PDN Tcl & tap/decap recipe; pinout CSV (bond map draft)
2Sat, 24 Jan 2026 – Fri, 30 Jan 2026Placement & pre‑CTS timingInsert tie/spare cells; global placement & legalization; clock plan (roots, skew target, buffer list); pre‑CTS opt: fix max tran/cap/fanout; pipeline/resize if needed; early RC (global route) for realistic timingPlaced DEF; pre‑CTS timing (max/min); congestion & utilization reports
3Sat, 31 Jan 2026 – Fri, 06 Feb 2026CTS, post‑CTS timing & SIRun CTS (balanced/useful skew); post‑CTS hold fixing; RC‑aware re‑opt (size/buffer); crosstalk mitigation; STA across TT/SS/FFPost‑CTS DEF; timing (setup/hold, clock summary); clock QoR (insertion, skew, buffer count)
4Sat, 07 Feb 2026 – Fri, 13 Feb 2026Route, antenna, fill, draft DRC/LVSGlobal + detailed route; antenna check/fix (diodes/jumps) & ECO route; metal density fill/slotting; first full‑chip DRC; prep LVSRouted DEF/GDS; antenna & density reports; first DRC/LVS logs
5Sat, 14 Feb 2026 – Fri, 20 Feb 2026Sign‑off PEX, STA, IR/EM, GLS/FEVGolden PEX → SPEF; sign‑off STA (all PVT + OCV/AOCV) & ECO; IR/EM; reinforce PG if needed; post‑layout GLS with SDF; formal equivalenceSPEF/SDF; sign‑off STA pack; IR/EM reports; GLS pass logs; FEV clean report
6Sat, 21 Feb 2026 – Fri, 27 Feb 2026Tapeout kit & submissionFinal DRC/LVS = 0 (or approved waivers); re‑fill after ECOs and re‑DRC; build tapeout package (GDSII, layer map, tech notes, netlist, LEF, reports, waivers); SCL jobdeck/forms; top‑cell checks; bonding/package kit & pinout CSV; golden re‑runsSubmission archive (GDSII + docs) & checklist; bonding/package kit

Tools & Infrastructure

  • Training Stack: iverilog, GTKWave, Yosys, OpenSTA, Xschem, ngspice, OpenLane
  • Sign‑off Stack: Synopsys (Design Compiler, PrimeTime, ICC2/Fusion), foundry DRC/LVS decks
  • PDK: SCL 180 nm (IO 2.5V, Core 1.8V), SRAM/POR macros
  • Collaboration: Git/GitHub for version control; reproducible Make/Tcl entrypoints

Delivery & Locations

  • Recruitment & Training is delivered online with hands‑on labs. Project Initialization (Top 50) runs on‑site at IIT Gandhinagar. Final GDSII & Tapeout (Top 20) is executed with Synopsys tools and SCL180 inputs under an industry‑style sign‑off regimen.
  • Project Initialization (Top 50) runs on‑site at IIT Gandhinagar.
  • Final GDSII & Tapeout (Top 20) is executed with Synopsys tools and SCL180 inputs under an industry‑style sign‑off regimen.

Eligibility & Prerequisites

  • Target Participants: Students, faculty, and engineers aiming to execute an academic‑grade RISC‑V SoC tapeout
  • Prerequisites: Basic RTL simulation, synthesis concepts, and comfort with Linux shell/Git; timing analysis fundamentals are helpful

Program Outcomes

  • Reusable RTL→GDSII flow with documented constraints and sign‑off artifacts
  • Corner‑clean timing reports (TT/SS/FF), SDF‑annotated GLS logs, and reproducible scripts
  • Tapeout submission package (GDSII + documentation) aligned with SCL requirements

Deliverables for Participants

  • Hardware: A taped-out RISC-V chip in QFN package.
  • Software: Embedded applications (IoT, edge compute).
  • Portfolio: GitHub repository with GDSII, testbenches, and docs.

Why Join This Project?

  • Industry Alignment: Use Synopsys EDA tools and SCL180 PDK.
  • Societal Impact: Low-cost chips for agriculture, healthcare, and smart devices.
  • Skill Advancement: Learn end-to-end RTL-to-GDSII flow.

How to Join?

Implicit Alignment with National Goals

  • 1. Skill Development: Trains students in cutting-edge EDA tools and fabless design.
  • 2. Collaborative R&D: Open-source IPs and shared workflows across institutions.
  • 3. Startup Enablement: Students can commercialize designs (e.g., IoT devices).
  • Supported By: Semiconductor Laboratory (SCL), Synopsys, VLSI System Design.
  • Contact: [email protected]
  • This structured, hands-on journey equips participants with industry-relevant skills while fostering innovation in strategic sectors. Let’s tape out!
  • Travel & Accommodation
  • 1) Travel and Food for top 50 candidates: self-funded by candidates
  • 2) Hostel Accommodation for Top 50 candidates for 3 Weeks- 10 Dec 25 - 1 Jan 2026
  • 3) Hostel Accommodation for Top 20 Candidates for 6 Weeks- 18 Jan - 27 Feb 2026

About VSD

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.

RISC‑V Reference SoC Tapeout Program

  • Registration closes on
  • 15th September 2025
  • Duration: 20 Weeks
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Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

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VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team. 

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VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach  ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.

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