VSD - Static Timing Analysis (STA) Webinar

Overview

VSD shows the technique to analyze a design using an Opentimer tool, which is used to do block-based analysis, path-based analysis, cppr, incremental timing, and multi-threading. Our methods are extremely fast and accurate to analyze large-scale designs.

• Entire STA flow and ECO flow
• Explore ideas and ways to implement automated ECO flow
• Calculate performance of your design, just the way industry works, and may be, get a feel of working in a semi-conductor industry.
• Open Source EDA tool installation & application
• Guide on How to analyze and design using OPHW tools
• Analyze design size, STA runtime & Performance Check
• ECO (Engineering change order)

This webinar highlights the merits of Open source EDA tools to bring innovation in the Chip industry, and will also show our methods to learn & design on your PC and also enables higher performance at zero cost.

Objectives

• Introduction to open-source C-to-GDS flow

• IC design components

  • RTL, floor-planning and power-planning
  • Placement and Clock tree synthesis
  • Introduction to static timing analysis (STA)
  • STA detailing
• Runtime theory and demo
  • Design size, RAM and runtime relationship
  • Runtime check demo using Opentimer
• Design speed and performance characterization
  • Worst negative slack (WNS) and total negative slack (TNS)
  • Introduction to term 'performance' and 'clock constraints'
  • IO constraints
  • Performance measurement using Opentimer Preview
• Timing libraries and engineering change order(ECO)
  • Brief description of timing libraries
  • Brief description about driver model and receiver model
  • Useful tips for operating frequency calculation
  • Hold ECO detailed steps with LIVE demo
• Assignment

Audience Profile

• Everyone who's interested in working on LIVE designs using open-source STA tool
• Everyone who want to know what's the structure of this industry, specially STA
• Everyone who would love to explore ways to innovate using open-source tools
• Everyone looking to work with me on LIVE project

Prerequisites

• Basics of Static Timing Analysis, not mandatory, as it will be anyways covered in this webinar
• Basics of digital gates and flip-flops

Tools Used

"Opentimer" open source tool developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA

Buy the course :

VSD - Static Timing Analysis (STA) WebinarKunal Ghosh, Digital and Sign-off expert at VLSI System Design(VSD)Characterize your design performance LIVE with me, just the way the industry works₹1,499₹549 4.3 (54 ratings)16 lectures, 2 hours