VSD-Hardware Design Program
SKY130-based ASIC design projects
The course introduces ASIC design flow, which is an iterative process but not static for every design. The base concepts remain the same, however, the details of the flow, like ECOs, IP requirements, DFT insertion, and SDC constraints, may change.
Below are the fundamental steps for ASIC design flow, which will be covered during the duration of the course:
- Architectural Design – A system engineer will provide the VLSI engineer with specifications for the system that are determined through physical constraints. The VLSI engineer will be required to design a circuit that meets these constraints at a microarchitecture modelling level.
- RTL Design/Behavioral Modeling – RTL design and behavioral modelling are performed with a hardware description language (HDL). EDA tools will use the HDL to perform mapping of higher-level components to the transistor level needed for physical implementation. HDL modelling is normally performed using either Verilog or VHDL. One of two design methods may be employed while creating the HDL of a microarchitecture
- RTL Verification – Behavioral verification of design
- Logic Synthesis – Logic synthesis uses the RTL netlist to perform HDL technology mapping.
- Post-Synthesis STA Analysis – Performs setup analysis on different path groups.
- Floorplanning – The goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. In addition, macro placement and blockages must be defined before placement occurs to ensure a legalized GDS file. In power planning, we create the ring which is connected to the pads and brings power around the edges of the chip. We also include power straps to bring power to the middle of the chip using higher metal layers which reduces IR drop and electro-migration problems.
- Placement – Place the standard cells on the floorplan rows, aligned with sites defined in the technology LEF file. Placement is done in two steps: Global and Detailed. Global placement tries to find the optimal position for all cells, but they may be overlapping and not aligned to rows, detailed placement takes the global placement and legalizes all the placements trying to adhere to what the global placement wants.
- CTS – Clock tree synthesis is used to create the clock distribution network that is used to deliver the clock to all sequential elements. The main goal is to create a network with minimal skew across the chip. H-trees are a common network topology that is used to achieve this goal.
- Routing – Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors.
We will use the OpenLANE RTL2GDS open-source EDA tool. OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, SPEF-Extractor and custom methodology scripts for design exploration and optimization. It is a tool started for true open-source tape-out experience and comes with APACHE version 2.0. The goal of OpenLANE is to produce clean GDSII without any human intervention. OpenLANE is tuned for Skywater 130nm open-source PDK and can be used to produce hard macros and chips.
Why is it important?
VLSI integrated circuits have revolutionized the industrial world. They are ubiquitous and are being deployed in every conceivable engineering system – from the simplest to the most complex. It is imperative to have the right skill sets amongst our graduating students to render these extremely complex chips efficiently and with a minimum number of re-spins as the Silicon processing steps to realize them have a very high cost.
The reason for using open-source EDA tools is to enable students to collaborate freely across organizations even after the course is over as there are no legal agreements to use open-source technology. With the advent of SKY130 PDKs, it enables easy access to tape-out shuttles which are currently sponsored by Google.
Below is the list of projects which a participant can choose during the HDP program.
Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the desired width. The duty cycle is the ratio of how long that PWM signal stays at the high position to the total period. This project simulates the designed Pulse Width Modulated Wave Generator with a Variable Duty Cycle. We can generate a PWM wave and vary its DUTY CYCLE in steps of 10%.
This project provides an insight into the working of a few important instructions of a Single cycle Reduced Instruction Set Computer – Five(RISC-V) Instruction Set Architecture suitable for use across a wide spectrum of applications from low-power embedded devices to high-performance Cloud-based Server processors. The base RISC-V ISA implementation is a 32-bit processor with 32 general-purpose registers. Some Applications where the RISC-V processors have begun to make some significant threads are Artificial intelligence and machine learning, Embedded systems, Ultra Low power processing systems etc.
In the current VLSI design, power dissipation is the most important parameter that signifies the need for low-power circuits. Most of the IC’s clock consumes 30-40 % of the total power. So, the integrated clock gating logic is used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use.
A frequency divider takes an input frequency and generated an output frequency depending on the division factor. One of the well-known applications of a frequency divider is a phase lock loop, which generates multiples of a reference frequency. The other applications include frequency synthesizers, audio equipment, radar and satellite communication, Military equipment, and RF devices.
The real-time circuit is interfaced with the microcontroller by Advanced Peripheral Bus following Advanced Microcontroller Bus Architecture (AMBA) bus protocol thereby communicating time with the microcontroller. A real-time clock provides an accurate time track to the device so all the events take place at the right time. This system functions reliably with optimum CPU and memory space usage.
A Universal Shift Register is a register with both right shift and left shift with parallel load capabilities. Universal Shift Registers are used as memory elements in computers. A Unidirectional Shift Register shifts in only one direction whereas a Bidirectional Shift Register can shift in both directions. The design of the Universal Shift Register is a combination of a Bidirectional Shift Register and a Unidirectional Shift Register with provision for parallel.
A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target sequence has been detected. In a sequence detector that allows overlap, the final bits of one sequence can be the start of another sequence. In Mealy, both the output and the next state depend on the present input and the present state. For the present state S0, if the input is ‘1’ then the next state is S1 and if the input is ‘0’ then the next state is the current state. It is like the present state S1. In the present state S2, if there is a false bit, the next state is S0 and in the present state S3, if there is a false bit, the next state is S1. It can be said that if there is a false input, the next state will be the nearest similar state.
This project simulates the Radix-2 4-Bit Booth’s Multiplier using Verilog HDL. It can be used to multiply two 4-bit binary signed numbers in an efficient manner with a smaller number of the addition operation. Booth’s Multiplier is based on Booth’s Multiplication Algorithm. It proposes an efficient way for multiplying two signed integers in their 2’s complement form such that the number of partial products is reduced which ultimately lead to the reduction of the number of addition operation required for generating the result.
Terms & Conditions:
If you are not available to attend the program, Raise refund request before the last day of registration date in Indian Standard Time zone for the training/workshop/design program.
( Last date to raise refund request– (19 October 2023 11:59 PM IST)
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