Hello
And you thought we are done with CPPR… No … not yet … We haven’t done the “Hold” analysis yet. Its simple, but its tricky. Why its simple? Its because of the amazing images that I use to describe things :).
Why its tricky? Let’s watch below. Its now ‘data arrival’ – ‘data required’ that needs to be positive, in contrast to ‘setup analysis’
With the below values assumed for the cell and net delays, we get a positive slack. Note : we haven’t accounted for OCV derates yet
We will, again, assume a 20% variation for OCV,
and do a more conservative hold analysis again, to observe how the positive slack becomes negative. This time we will ‘Pull-in’ the launch clock by 20% and ‘Push-out’ the capture clock by 20%.
Why we do this? We just need to be extra careful for hold analysis, and its just a single edge check. I will get back to this in my upcoming post
Here we get a negative slack, and a negative slack in hold is like your LIFE. Needs to be taken seriously :).
There are still ways to recover from a setup violation, but there are no ways to recover from a hold violation (in a specific PVT corner). I will talk more about this in my upcoming posts.
Below shows original and 20% derated delay side-by-side
Ahh… STA engineers just hate this part of -ve hold violations. And it’s really annoying, if this is seen towards end of release.
But …. Hello …. Catch ….. Common Clock Path …. 2 different delays …. not possible …. blinks a light ….. previous post …..
The happy part, we will remove the additional pessimism, …..
And…. Bang ….. There you go … you just got rid of those nasty hold violations, smartly
This completes the basic CPPR, and should be good enough to get you started with your critical timing analysis. And if these concepts on CPPR help you, donot forget to send a note to me …. 🙂
And if this is not enough, go through my CPPR videos on YouTube…..
https://www.youtube.com/playlist?list=PLUSK3BZWA60uEbKzWP6SST8MwkQ-0GOrs
Good Bye for now… I will be back with some more interesting concepts, next time
Thanks
Kunal
